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M4521_BSP V3.01.001
The Board Support Package for M4521
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#include "core_cm4.h"#include "system_M4521.h"#include <stdint.h>#include "sys.h"#include "clk.h"#include "gpio.h"#include "i2c.h"#include "crc.h"#include "ebi.h"#include "rtc.h"#include "timer.h"#include "wdt.h"#include "wwdt.h"#include "spi.h"#include "sc.h"#include "scuart.h"#include "eadc.h"#include "usbd.h"#include "fmc.h"#include "uart.h"#include "pwm.h"#include "pdma.h"

Go to the source code of this file.
Data Structures | |
| struct | EADC_T |
| struct | CLK_T |
| struct | CRC_T |
| struct | EBI_T |
| struct | FMC_T |
| struct | GPIO_T |
| struct | GPIO_DBCTL_T |
| struct | I2C_T |
| struct | DSCT_T |
| struct | PDMA_T |
| struct | PWM_T |
| struct | RTC_T |
| struct | SC_T |
| struct | SPI_T |
| struct | SYS_T |
| struct | SYS_INT_T |
| struct | TIMER_T |
| struct | UART_T |
| struct | USBD_EP_T |
| USBD endpoints register. More... | |
| struct | USBD_T |
| struct | USBH_T |
| struct | WDT_T |
| struct | WWDT_T |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
| typedef volatile unsigned char | vu8 |
| typedef volatile unsigned long | vu32 |
| typedef volatile unsigned short | vu16 |
| #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) |
CRC_T::CHECKSUM: CHECKSUM Mask
| #define CRC_CHECKSUM_CHECKSUM_Pos (0) |
CRC_T::CHECKSUM: CHECKSUM Position
| #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) |
CRC_T::CTL: CHKSFMT Mask
| #define CRC_CTL_CHKSFMT_Pos (27) |
CRC_T::CTL: CHKSFMT Position
| #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) |
CRC_T::CTL: CHKSREV Mask
| #define CRC_CTL_CHKSREV_Pos (25) |
CRC_T::CTL: CHKSREV Position
| #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) |
CRC_T::CTL: CRCEN Mask
| #define CRC_CTL_CRCEN_Pos (0) |
@addtogroup CRC_CONST CRC Bit Field Definition Constant Definitions for CRC Controller
CRC_T::CTL: CRCEN Position
| #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) |
CRC_T::CTL: CRCMODE Mask
| #define CRC_CTL_CRCMODE_Pos (30) |
CRC_T::CTL: CRCMODE Position
| #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) |
CRC_T::CTL: CRCRST Mask
| #define CRC_CTL_CRCRST_Pos (1) |
CRC_T::CTL: CRCRST Position
| #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) |
CRC_T::CTL: DATFMT Mask
| #define CRC_CTL_DATFMT_Pos (26) |
CRC_T::CTL: DATFMT Position
| #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) |
CRC_T::CTL: DATLEN Mask
| #define CRC_CTL_DATLEN_Pos (28) |
CRC_T::CTL: DATLEN Position
| #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) |
CRC_T::CTL: DATREV Mask
| #define CRC_CTL_DATREV_Pos (24) |
CRC_T::CTL: DATREV Position
| #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) |
CRC_T::DAT: DATA Mask
| #define CRC_DAT_DATA_Pos (0) |
CRC_T::DAT: DATA Position
| #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) |
CRC_T::SEED: SEED Mask
| #define CRC_SEED_SEED_Pos (0) |
CRC_T::SEED: SEED Position
| #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) |
EBI_T::CTL0: CSPOLINV Mask
| #define EBI_CTL0_CSPOLINV_Pos (2) |
EBI_T::CTL0: CSPOLINV Position
| #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) |
EBI_T::CTL0: DW16 Mask
| #define EBI_CTL0_DW16_Pos (1) |
EBI_T::CTL0: DW16 Position
| #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) |
EBI_T::CTL0: EN Mask
| #define EBI_CTL0_EN_Pos (0) |
@addtogroup EBI_CONST EBI Bit Field Definition Constant Definitions for EBI Controller
EBI_T::CTL0: EN Position
| #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) |
EBI_T::CTL0: MCLKDIV Mask
| #define EBI_CTL0_MCLKDIV_Pos (8) |
EBI_T::CTL0: MCLKDIV Position
| #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) |
EBI_T::CTL0: TALE Mask
| #define EBI_CTL0_TALE_Pos (16) |
EBI_T::CTL0: TALE Position
| #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) |
EBI_T::CTL0: WBUFEN Mask
| #define EBI_CTL0_WBUFEN_Pos (24) |
EBI_T::CTL0: WBUFEN Position
| #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) |
EBI_T::CTL1: CSPOLINV Mask
| #define EBI_CTL1_CSPOLINV_Pos (2) |
EBI_T::CTL1: CSPOLINV Position
| #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) |
EBI_T::CTL1: DW16 Mask
| #define EBI_CTL1_DW16_Pos (1) |
EBI_T::CTL1: DW16 Position
| #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) |
EBI_T::CTL1: EN Mask
| #define EBI_CTL1_EN_Pos (0) |
EBI_T::CTL1: EN Position
| #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) |
EBI_T::CTL1: MCLKDIV Mask
| #define EBI_CTL1_MCLKDIV_Pos (8) |
EBI_T::CTL1: MCLKDIV Position
| #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) |
EBI_T::CTL1: TALE Mask
| #define EBI_CTL1_TALE_Pos (16) |
EBI_T::CTL1: TALE Position
| #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) |
EBI_T::CTL1: WBUFEN Mask
| #define EBI_CTL1_WBUFEN_Pos (24) |
EBI_T::CTL1: WBUFEN Position
| #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) |
EBI_T::TCTL0: R2R Mask
| #define EBI_TCTL0_R2R_Pos (24) |
EBI_T::TCTL0: R2R Position
| #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) |
EBI_T::TCTL0: RAHDOFF Mask
| #define EBI_TCTL0_RAHDOFF_Pos (22) |
EBI_T::TCTL0: RAHDOFF Position
| #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) |
EBI_T::TCTL0: TACC Mask
| #define EBI_TCTL0_TACC_Pos (3) |
EBI_T::TCTL0: TACC Position
| #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) |
EBI_T::TCTL0: TAHD Mask
| #define EBI_TCTL0_TAHD_Pos (8) |
EBI_T::TCTL0: TAHD Position
| #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) |
EBI_T::TCTL0: W2X Mask
| #define EBI_TCTL0_W2X_Pos (12) |
EBI_T::TCTL0: W2X Position
| #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) |
EBI_T::TCTL0: WAHDOFF Mask
| #define EBI_TCTL0_WAHDOFF_Pos (23) |
EBI_T::TCTL0: WAHDOFF Position
| #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) |
EBI_T::TCTL1: R2R Mask
| #define EBI_TCTL1_R2R_Pos (24) |
EBI_T::TCTL1: R2R Position
| #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) |
EBI_T::TCTL1: RAHDOFF Mask
| #define EBI_TCTL1_RAHDOFF_Pos (22) |
EBI_T::TCTL1: RAHDOFF Position
| #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) |
EBI_T::TCTL1: TACC Mask
| #define EBI_TCTL1_TACC_Pos (3) |
EBI_T::TCTL1: TACC Position
| #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) |
EBI_T::TCTL1: TAHD Mask
| #define EBI_TCTL1_TAHD_Pos (8) |
EBI_T::TCTL1: TAHD Position
| #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) |
EBI_T::TCTL1: W2X Mask
| #define EBI_TCTL1_W2X_Pos (12) |
EBI_T::TCTL1: W2X Position
| #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) |
EBI_T::TCTL1: WAHDOFF Mask
| #define EBI_TCTL1_WAHDOFF_Pos (23) |
EBI_T::TCTL1: WAHDOFF Position
| #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
FMC_T::DFBA: DFBA Mask
| #define FMC_DFBA_DFBA_Pos (0) |
FMC_T::DFBA: DFBA Position
| #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) |
FMC_T::FTCTL: FOM Mask
| #define FMC_FTCTL_FOM_Pos (4) |
FMC_T::FTCTL: FOM Position
| #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
FMC_T::ISPADDR: ISPADDR Mask
| #define FMC_ISPADDR_ISPADDR_Pos (0) |
FMC_T::ISPADDR: ISPADDR Position
| #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) |
FMC_T::ISPCMD: CMD Mask
| #define FMC_ISPCMD_CMD_Pos (0) |
FMC_T::ISPCMD: CMD Position
| #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
FMC_T::ISPCTL: APUEN Mask
| #define FMC_ISPCTL_APUEN_Pos (3) |
FMC_T::ISPCTL: APUEN Position
| #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) |
FMC_T::ISPCTL: BL Mask
| #define FMC_ISPCTL_BL_Pos (16) |
FMC_T::ISPCTL: BL Position
| #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
FMC_T::ISPCTL: BS Mask
| #define FMC_ISPCTL_BS_Pos (1) |
FMC_T::ISPCTL: BS Position
| #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
FMC_T::ISPCTL: CFGUEN Mask
| #define FMC_ISPCTL_CFGUEN_Pos (4) |
FMC_T::ISPCTL: CFGUEN Position
| #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
FMC_T::ISPCTL: ISPEN Mask
| #define FMC_ISPCTL_ISPEN_Pos (0) |
@addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller
FMC_T::ISPCTL: ISPEN Position
| #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
FMC_T::ISPCTL: ISPFF Mask
| #define FMC_ISPCTL_ISPFF_Pos (6) |
FMC_T::ISPCTL: ISPFF Position
| #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
FMC_T::ISPCTL: LDUEN Mask
| #define FMC_ISPCTL_LDUEN_Pos (5) |
FMC_T::ISPCTL: LDUEN Position
| #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
FMC_T::ISPDAT: ISPDAT Mask
| #define FMC_ISPDAT_ISPDAT_Pos (0) |
FMC_T::ISPDAT: ISPDAT Position
| #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
FMC_T::ISPSTS: CBS Mask
| #define FMC_ISPSTS_CBS_Pos (1) |
FMC_T::ISPSTS: CBS Position
| #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
FMC_T::ISPSTS: ISPBUSY Mask
| #define FMC_ISPSTS_ISPBUSY_Pos (0) |
FMC_T::ISPSTS: ISPBUSY Position
| #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
FMC_T::ISPSTS: ISPFF Mask
| #define FMC_ISPSTS_ISPFF_Pos (6) |
FMC_T::ISPSTS: ISPFF Position
| #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) |
FMC_T::ISPSTS: MBS Mask
| #define FMC_ISPSTS_MBS_Pos (3) |
FMC_T::ISPSTS: MBS Position
| #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) |
FMC_T::ISPSTS: PGFF Mask
| #define FMC_ISPSTS_PGFF_Pos (5) |
FMC_T::ISPSTS: PGFF Position
| #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) |
FMC_T::ISPSTS: VECMAP Mask
| #define FMC_ISPSTS_VECMAP_Pos (9) |
FMC_T::ISPSTS: VECMAP Position
| #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
FMC_T::ISPTRG: ISPGO Mask
| #define FMC_ISPTRG_ISPGO_Pos (0) |
FMC_T::ISPTRG: ISPGO Position
| #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) |
FMC_T::MPADDR: MPADDR Mask
| #define FMC_MPADDR_MPADDR_Pos (0) |
FMC_T::MPADDR: MPADDR Position
| #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) |
FMC_T::MPDAT0: ISPDAT0 Mask
| #define FMC_MPDAT0_ISPDAT0_Pos (0) |
FMC_T::MPDAT0: ISPDAT0 Position
| #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) |
FMC_T::MPDAT1: ISPDAT1 Mask
| #define FMC_MPDAT1_ISPDAT1_Pos (0) |
FMC_T::MPDAT1: ISPDAT1 Position
| #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) |
FMC_T::MPDAT2: ISPDAT2 Mask
| #define FMC_MPDAT2_ISPDAT2_Pos (0) |
FMC_T::MPDAT2: ISPDAT2 Position
| #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) |
FMC_T::MPDAT3: ISPDAT3 Mask
| #define FMC_MPDAT3_ISPDAT3_Pos (0) |
FMC_T::MPDAT3: ISPDAT3 Position
| #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) |
FMC_T::MPSTS: D0 Mask
| #define FMC_MPSTS_D0_Pos (4) |
FMC_T::MPSTS: D0 Position
| #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) |
FMC_T::MPSTS: D1 Mask
| #define FMC_MPSTS_D1_Pos (5) |
FMC_T::MPSTS: D1 Position
| #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) |
FMC_T::MPSTS: D2 Mask
| #define FMC_MPSTS_D2_Pos (6) |
FMC_T::MPSTS: D2 Position
| #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) |
FMC_T::MPSTS: D3 Mask
| #define FMC_MPSTS_D3_Pos (7) |
FMC_T::MPSTS: D3 Position
| #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) |
FMC_T::MPSTS: ISPFF Mask
| #define FMC_MPSTS_ISPFF_Pos (2) |
FMC_T::MPSTS: ISPFF Position
| #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) |
FMC_T::MPSTS: MPBUSY Mask
| #define FMC_MPSTS_MPBUSY_Pos (0) |
FMC_T::MPSTS: MPBUSY Position
| #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) |
FMC_T::MPSTS: PPGO Mask
| #define FMC_MPSTS_PPGO_Pos (1) |
FMC_T::MPSTS: PPGO Position
| #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) |
GPIO_T::DATMSK: DMASK0 Mask
| #define GPIO_DATMSK_DMASK0_Pos (0) |
GPIO_T::DATMSK: DMASK0 Position
| #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) |
GPIO_T::DATMSK: DMASK10 Mask
| #define GPIO_DATMSK_DMASK10_Pos (10) |
GPIO_T::DATMSK: DMASK10 Position
| #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) |
GPIO_T::DATMSK: DMASK11 Mask
| #define GPIO_DATMSK_DMASK11_Pos (11) |
GPIO_T::DATMSK: DMASK11 Position
| #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) |
GPIO_T::DATMSK: DMASK12 Mask
| #define GPIO_DATMSK_DMASK12_Pos (12) |
GPIO_T::DATMSK: DMASK12 Position
| #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) |
GPIO_T::DATMSK: DMASK13 Mask
| #define GPIO_DATMSK_DMASK13_Pos (13) |
GPIO_T::DATMSK: DMASK13 Position
| #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) |
GPIO_T::DATMSK: DMASK14 Mask
| #define GPIO_DATMSK_DMASK14_Pos (14) |
GPIO_T::DATMSK: DMASK14 Position
| #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) |
GPIO_T::DATMSK: DMASK15 Mask
| #define GPIO_DATMSK_DMASK15_Pos (15) |
GPIO_T::DATMSK: DMASK15 Position
| #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) |
GPIO_T::DATMSK: DMASK1 Mask
| #define GPIO_DATMSK_DMASK1_Pos (1) |
GPIO_T::DATMSK: DMASK1 Position
| #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) |
GPIO_T::DATMSK: DMASK2 Mask
| #define GPIO_DATMSK_DMASK2_Pos (2) |
GPIO_T::DATMSK: DMASK2 Position
| #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) |
GPIO_T::DATMSK: DMASK3 Mask
| #define GPIO_DATMSK_DMASK3_Pos (3) |
GPIO_T::DATMSK: DMASK3 Position
| #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) |
GPIO_T::DATMSK: DMASK4 Mask
| #define GPIO_DATMSK_DMASK4_Pos (4) |
GPIO_T::DATMSK: DMASK4 Position
| #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) |
GPIO_T::DATMSK: DMASK5 Mask
| #define GPIO_DATMSK_DMASK5_Pos (5) |
GPIO_T::DATMSK: DMASK5 Position
| #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) |
GPIO_T::DATMSK: DMASK6 Mask
| #define GPIO_DATMSK_DMASK6_Pos (6) |
GPIO_T::DATMSK: DMASK6 Position
| #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) |
GPIO_T::DATMSK: DMASK7 Mask
| #define GPIO_DATMSK_DMASK7_Pos (7) |
GPIO_T::DATMSK: DMASK7 Position
| #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) |
GPIO_T::DATMSK: DMASK8 Mask
| #define GPIO_DATMSK_DMASK8_Pos (8) |
GPIO_T::DATMSK: DMASK8 Position
| #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) |
GPIO_T::DATMSK: DMASK9 Mask
| #define GPIO_DATMSK_DMASK9_Pos (9) |
GPIO_T::DATMSK: DMASK9 Position
| #define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) |
| #define GPIO_DBCTL_DBCLKSEL_Pos (0) |
| #define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
| #define GPIO_DBCTL_DBCLKSRC_Pos (4) |
| #define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) |
| #define GPIO_DBCTL_ICLKON_Pos (5) |
| #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
GPIO_T::DBEN: DBEN0 Mask
| #define GPIO_DBEN_DBEN0_Pos (0) |
GPIO_T::DBEN: DBEN0 Position
| #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
GPIO_T::DBEN: DBEN10 Mask
| #define GPIO_DBEN_DBEN10_Pos (10) |
GPIO_T::DBEN: DBEN10 Position
| #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
GPIO_T::DBEN: DBEN11 Mask
| #define GPIO_DBEN_DBEN11_Pos (11) |
GPIO_T::DBEN: DBEN11 Position
| #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
GPIO_T::DBEN: DBEN12 Mask
| #define GPIO_DBEN_DBEN12_Pos (12) |
GPIO_T::DBEN: DBEN12 Position
| #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
GPIO_T::DBEN: DBEN13 Mask
| #define GPIO_DBEN_DBEN13_Pos (13) |
GPIO_T::DBEN: DBEN13 Position
| #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
GPIO_T::DBEN: DBEN14 Mask
| #define GPIO_DBEN_DBEN14_Pos (14) |
GPIO_T::DBEN: DBEN14 Position
| #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
GPIO_T::DBEN: DBEN15 Mask
| #define GPIO_DBEN_DBEN15_Pos (15) |
GPIO_T::DBEN: DBEN15 Position
| #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
GPIO_T::DBEN: DBEN1 Mask
| #define GPIO_DBEN_DBEN1_Pos (1) |
GPIO_T::DBEN: DBEN1 Position
| #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
GPIO_T::DBEN: DBEN2 Mask
| #define GPIO_DBEN_DBEN2_Pos (2) |
GPIO_T::DBEN: DBEN2 Position
| #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
GPIO_T::DBEN: DBEN3 Mask
| #define GPIO_DBEN_DBEN3_Pos (3) |
GPIO_T::DBEN: DBEN3 Position
| #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
GPIO_T::DBEN: DBEN4 Mask
| #define GPIO_DBEN_DBEN4_Pos (4) |
GPIO_T::DBEN: DBEN4 Position
| #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
GPIO_T::DBEN: DBEN5 Mask
| #define GPIO_DBEN_DBEN5_Pos (5) |
GPIO_T::DBEN: DBEN5 Position
| #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
GPIO_T::DBEN: DBEN6 Mask
| #define GPIO_DBEN_DBEN6_Pos (6) |
GPIO_T::DBEN: DBEN6 Position
| #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
GPIO_T::DBEN: DBEN7 Mask
| #define GPIO_DBEN_DBEN7_Pos (7) |
GPIO_T::DBEN: DBEN7 Position
| #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
GPIO_T::DBEN: DBEN8 Mask
| #define GPIO_DBEN_DBEN8_Pos (8) |
GPIO_T::DBEN: DBEN8 Position
| #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
GPIO_T::DBEN: DBEN9 Mask
| #define GPIO_DBEN_DBEN9_Pos (9) |
GPIO_T::DBEN: DBEN9 Position
| #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
GPIO_T::DINOFF: DINOFF0 Mask
| #define GPIO_DINOFF_DINOFF0_Pos (16) |
GPIO_T::DINOFF: DINOFF0 Position
| #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
GPIO_T::DINOFF: DINOFF10 Mask
| #define GPIO_DINOFF_DINOFF10_Pos (26) |
GPIO_T::DINOFF: DINOFF10 Position
| #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
GPIO_T::DINOFF: DINOFF11 Mask
| #define GPIO_DINOFF_DINOFF11_Pos (27) |
GPIO_T::DINOFF: DINOFF11 Position
| #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
GPIO_T::DINOFF: DINOFF12 Mask
| #define GPIO_DINOFF_DINOFF12_Pos (28) |
GPIO_T::DINOFF: DINOFF12 Position
| #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
GPIO_T::DINOFF: DINOFF13 Mask
| #define GPIO_DINOFF_DINOFF13_Pos (29) |
GPIO_T::DINOFF: DINOFF13 Position
| #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
GPIO_T::DINOFF: DINOFF14 Mask
| #define GPIO_DINOFF_DINOFF14_Pos (30) |
GPIO_T::DINOFF: DINOFF14 Position
| #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
GPIO_T::DINOFF: DINOFF15 Mask
| #define GPIO_DINOFF_DINOFF15_Pos (31) |
GPIO_T::DINOFF: DINOFF15 Position
| #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
GPIO_T::DINOFF: DINOFF1 Mask
| #define GPIO_DINOFF_DINOFF1_Pos (17) |
GPIO_T::DINOFF: DINOFF1 Position
| #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
GPIO_T::DINOFF: DINOFF2 Mask
| #define GPIO_DINOFF_DINOFF2_Pos (18) |
GPIO_T::DINOFF: DINOFF2 Position
| #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
GPIO_T::DINOFF: DINOFF3 Mask
| #define GPIO_DINOFF_DINOFF3_Pos (19) |
GPIO_T::DINOFF: DINOFF3 Position
| #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
GPIO_T::DINOFF: DINOFF4 Mask
| #define GPIO_DINOFF_DINOFF4_Pos (20) |
GPIO_T::DINOFF: DINOFF4 Position
| #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
GPIO_T::DINOFF: DINOFF5 Mask
| #define GPIO_DINOFF_DINOFF5_Pos (21) |
GPIO_T::DINOFF: DINOFF5 Position
| #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
GPIO_T::DINOFF: DINOFF6 Mask
| #define GPIO_DINOFF_DINOFF6_Pos (22) |
GPIO_T::DINOFF: DINOFF6 Position
| #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
GPIO_T::DINOFF: DINOFF7 Mask
| #define GPIO_DINOFF_DINOFF7_Pos (23) |
GPIO_T::DINOFF: DINOFF7 Position
| #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
GPIO_T::DINOFF: DINOFF8 Mask
| #define GPIO_DINOFF_DINOFF8_Pos (24) |
GPIO_T::DINOFF: DINOFF8 Position
| #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
GPIO_T::DINOFF: DINOFF9 Mask
| #define GPIO_DINOFF_DINOFF9_Pos (25) |
GPIO_T::DINOFF: DINOFF9 Position
| #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
GPIO_T::DOUT: DOUT0 Mask
| #define GPIO_DOUT_DOUT0_Pos (0) |
GPIO_T::DOUT: DOUT0 Position
| #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
GPIO_T::DOUT: DOUT10 Mask
| #define GPIO_DOUT_DOUT10_Pos (10) |
GPIO_T::DOUT: DOUT10 Position
| #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
GPIO_T::DOUT: DOUT11 Mask
| #define GPIO_DOUT_DOUT11_Pos (11) |
GPIO_T::DOUT: DOUT11 Position
| #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
GPIO_T::DOUT: DOUT12 Mask
| #define GPIO_DOUT_DOUT12_Pos (12) |
GPIO_T::DOUT: DOUT12 Position
| #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
GPIO_T::DOUT: DOUT13 Mask
| #define GPIO_DOUT_DOUT13_Pos (13) |
GPIO_T::DOUT: DOUT13 Position
| #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
GPIO_T::DOUT: DOUT14 Mask
| #define GPIO_DOUT_DOUT14_Pos (14) |
GPIO_T::DOUT: DOUT14 Position
| #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
GPIO_T::DOUT: DOUT15 Mask
| #define GPIO_DOUT_DOUT15_Pos (15) |
GPIO_T::DOUT: DOUT15 Position
| #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
GPIO_T::DOUT: DOUT1 Mask
| #define GPIO_DOUT_DOUT1_Pos (1) |
GPIO_T::DOUT: DOUT1 Position
| #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
GPIO_T::DOUT: DOUT2 Mask
| #define GPIO_DOUT_DOUT2_Pos (2) |
GPIO_T::DOUT: DOUT2 Position
| #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
GPIO_T::DOUT: DOUT3 Mask
| #define GPIO_DOUT_DOUT3_Pos (3) |
GPIO_T::DOUT: DOUT3 Position
| #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
GPIO_T::DOUT: DOUT4 Mask
| #define GPIO_DOUT_DOUT4_Pos (4) |
GPIO_T::DOUT: DOUT4 Position
| #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
GPIO_T::DOUT: DOUT5 Mask
| #define GPIO_DOUT_DOUT5_Pos (5) |
GPIO_T::DOUT: DOUT5 Position
| #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
GPIO_T::DOUT: DOUT6 Mask
| #define GPIO_DOUT_DOUT6_Pos (6) |
GPIO_T::DOUT: DOUT6 Position
| #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
GPIO_T::DOUT: DOUT7 Mask
| #define GPIO_DOUT_DOUT7_Pos (7) |
GPIO_T::DOUT: DOUT7 Position
| #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
GPIO_T::DOUT: DOUT8 Mask
| #define GPIO_DOUT_DOUT8_Pos (8) |
GPIO_T::DOUT: DOUT8 Position
| #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
GPIO_T::DOUT: DOUT9 Mask
| #define GPIO_DOUT_DOUT9_Pos (9) |
GPIO_T::DOUT: DOUT9 Position
| #define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) |
GPIO_T::DRVCTL: HDRVEN10 Mask
| #define GPIO_DRVCTL_HDRVEN10_Pos (10) |
GPIO_T::DRVCTL: HDRVEN10 Position
| #define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) |
GPIO_T::DRVCTL: HDRVEN11 Mask
| #define GPIO_DRVCTL_HDRVEN11_Pos (11) |
GPIO_T::DRVCTL: HDRVEN11 Position
| #define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) |
GPIO_T::DRVCTL: HDRVEN12 Mask
| #define GPIO_DRVCTL_HDRVEN12_Pos (12) |
GPIO_T::DRVCTL: HDRVEN12 Position
| #define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) |
GPIO_T::DRVCTL: HDRVEN13 Mask
| #define GPIO_DRVCTL_HDRVEN13_Pos (13) |
GPIO_T::DRVCTL: HDRVEN13 Position
| #define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) |
GPIO_T::DRVCTL: HDRVEN8 Mask
| #define GPIO_DRVCTL_HDRVEN8_Pos (8) |
GPIO_T::DRVCTL: HDRVEN8 Position
| #define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) |
GPIO_T::DRVCTL: HDRVEN9 Mask
| #define GPIO_DRVCTL_HDRVEN9_Pos (9) |
GPIO_T::DRVCTL: HDRVEN9 Position
| #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
GPIO_T::INTEN: FLIEN0 Mask
| #define GPIO_INTEN_FLIEN0_Pos (0) |
GPIO_T::INTEN: FLIEN0 Position
| #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
GPIO_T::INTEN: FLIEN10 Mask
| #define GPIO_INTEN_FLIEN10_Pos (10) |
GPIO_T::INTEN: FLIEN10 Position
| #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
GPIO_T::INTEN: FLIEN11 Mask
| #define GPIO_INTEN_FLIEN11_Pos (11) |
GPIO_T::INTEN: FLIEN11 Position
| #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
GPIO_T::INTEN: FLIEN12 Mask
| #define GPIO_INTEN_FLIEN12_Pos (12) |
GPIO_T::INTEN: FLIEN12 Position
| #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
GPIO_T::INTEN: FLIEN13 Mask
| #define GPIO_INTEN_FLIEN13_Pos (13) |
GPIO_T::INTEN: FLIEN13 Position
| #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
GPIO_T::INTEN: FLIEN14 Mask
| #define GPIO_INTEN_FLIEN14_Pos (14) |
GPIO_T::INTEN: FLIEN14 Position
| #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
GPIO_T::INTEN: FLIEN15 Mask
| #define GPIO_INTEN_FLIEN15_Pos (15) |
GPIO_T::INTEN: FLIEN15 Position
| #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
GPIO_T::INTEN: FLIEN1 Mask
| #define GPIO_INTEN_FLIEN1_Pos (1) |
GPIO_T::INTEN: FLIEN1 Position
| #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
GPIO_T::INTEN: FLIEN2 Mask
| #define GPIO_INTEN_FLIEN2_Pos (2) |
GPIO_T::INTEN: FLIEN2 Position
| #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
GPIO_T::INTEN: FLIEN3 Mask
| #define GPIO_INTEN_FLIEN3_Pos (3) |
GPIO_T::INTEN: FLIEN3 Position
| #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
GPIO_T::INTEN: FLIEN4 Mask
| #define GPIO_INTEN_FLIEN4_Pos (4) |
GPIO_T::INTEN: FLIEN4 Position
| #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
GPIO_T::INTEN: FLIEN5 Mask
| #define GPIO_INTEN_FLIEN5_Pos (5) |
GPIO_T::INTEN: FLIEN5 Position
| #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
GPIO_T::INTEN: FLIEN6 Mask
| #define GPIO_INTEN_FLIEN6_Pos (6) |
GPIO_T::INTEN: FLIEN6 Position
| #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
GPIO_T::INTEN: FLIEN7 Mask
| #define GPIO_INTEN_FLIEN7_Pos (7) |
GPIO_T::INTEN: FLIEN7 Position
| #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
GPIO_T::INTEN: FLIEN8 Mask
| #define GPIO_INTEN_FLIEN8_Pos (8) |
GPIO_T::INTEN: FLIEN8 Position
| #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
GPIO_T::INTEN: FLIEN9 Mask
| #define GPIO_INTEN_FLIEN9_Pos (9) |
GPIO_T::INTEN: FLIEN9 Position
| #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
GPIO_T::INTEN: RHIEN0 Mask
| #define GPIO_INTEN_RHIEN0_Pos (16) |
GPIO_T::INTEN: RHIEN0 Position
| #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
GPIO_T::INTEN: RHIEN10 Mask
| #define GPIO_INTEN_RHIEN10_Pos (26) |
GPIO_T::INTEN: RHIEN10 Position
| #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
GPIO_T::INTEN: RHIEN11 Mask
| #define GPIO_INTEN_RHIEN11_Pos (27) |
GPIO_T::INTEN: RHIEN11 Position
| #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
GPIO_T::INTEN: RHIEN12 Mask
| #define GPIO_INTEN_RHIEN12_Pos (28) |
GPIO_T::INTEN: RHIEN12 Position
| #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
GPIO_T::INTEN: RHIEN13 Mask
| #define GPIO_INTEN_RHIEN13_Pos (29) |
GPIO_T::INTEN: RHIEN13 Position
| #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
GPIO_T::INTEN: RHIEN14 Mask
| #define GPIO_INTEN_RHIEN14_Pos (30) |
GPIO_T::INTEN: RHIEN14 Position
| #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
GPIO_T::INTEN: RHIEN15 Mask
| #define GPIO_INTEN_RHIEN15_Pos (31) |
GPIO_T::INTEN: RHIEN15 Position
| #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
GPIO_T::INTEN: RHIEN1 Mask
| #define GPIO_INTEN_RHIEN1_Pos (17) |
GPIO_T::INTEN: RHIEN1 Position
| #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
GPIO_T::INTEN: RHIEN2 Mask
| #define GPIO_INTEN_RHIEN2_Pos (18) |
GPIO_T::INTEN: RHIEN2 Position
| #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
GPIO_T::INTEN: RHIEN3 Mask
| #define GPIO_INTEN_RHIEN3_Pos (19) |
GPIO_T::INTEN: RHIEN3 Position
| #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
GPIO_T::INTEN: RHIEN4 Mask
| #define GPIO_INTEN_RHIEN4_Pos (20) |
GPIO_T::INTEN: RHIEN4 Position
| #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
GPIO_T::INTEN: RHIEN5 Mask
| #define GPIO_INTEN_RHIEN5_Pos (21) |
GPIO_T::INTEN: RHIEN5 Position
| #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
GPIO_T::INTEN: RHIEN6 Mask
| #define GPIO_INTEN_RHIEN6_Pos (22) |
GPIO_T::INTEN: RHIEN6 Position
| #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
GPIO_T::INTEN: RHIEN7 Mask
| #define GPIO_INTEN_RHIEN7_Pos (23) |
GPIO_T::INTEN: RHIEN7 Position
| #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
GPIO_T::INTEN: RHIEN8 Mask
| #define GPIO_INTEN_RHIEN8_Pos (24) |
GPIO_T::INTEN: RHIEN8 Position
| #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
GPIO_T::INTEN: RHIEN9 Mask
| #define GPIO_INTEN_RHIEN9_Pos (25) |
GPIO_T::INTEN: RHIEN9 Position
| #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
GPIO_T::INTSRC: INTSRC0 Mask
| #define GPIO_INTSRC_INTSRC0_Pos (0) |
GPIO_T::INTSRC: INTSRC0 Position
| #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
GPIO_T::INTSRC: INTSRC10 Mask
| #define GPIO_INTSRC_INTSRC10_Pos (10) |
GPIO_T::INTSRC: INTSRC10 Position
| #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
GPIO_T::INTSRC: INTSRC11 Mask
| #define GPIO_INTSRC_INTSRC11_Pos (11) |
GPIO_T::INTSRC: INTSRC11 Position
| #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
GPIO_T::INTSRC: INTSRC12 Mask
| #define GPIO_INTSRC_INTSRC12_Pos (12) |
GPIO_T::INTSRC: INTSRC12 Position
| #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
GPIO_T::INTSRC: INTSRC13 Mask
| #define GPIO_INTSRC_INTSRC13_Pos (13) |
GPIO_T::INTSRC: INTSRC13 Position
| #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
GPIO_T::INTSRC: INTSRC14 Mask
| #define GPIO_INTSRC_INTSRC14_Pos (14) |
GPIO_T::INTSRC: INTSRC14 Position
| #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
GPIO_T::INTSRC: INTSRC15 Mask
| #define GPIO_INTSRC_INTSRC15_Pos (15) |
GPIO_T::INTSRC: INTSRC15 Position
| #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
GPIO_T::INTSRC: INTSRC1 Mask
| #define GPIO_INTSRC_INTSRC1_Pos (1) |
GPIO_T::INTSRC: INTSRC1 Position
| #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
GPIO_T::INTSRC: INTSRC2 Mask
| #define GPIO_INTSRC_INTSRC2_Pos (2) |
GPIO_T::INTSRC: INTSRC2 Position
| #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
GPIO_T::INTSRC: INTSRC3 Mask
| #define GPIO_INTSRC_INTSRC3_Pos (3) |
GPIO_T::INTSRC: INTSRC3 Position
| #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
GPIO_T::INTSRC: INTSRC4 Mask
| #define GPIO_INTSRC_INTSRC4_Pos (4) |
GPIO_T::INTSRC: INTSRC4 Position
| #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
GPIO_T::INTSRC: INTSRC5 Mask
| #define GPIO_INTSRC_INTSRC5_Pos (5) |
GPIO_T::INTSRC: INTSRC5 Position
| #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
GPIO_T::INTSRC: INTSRC6 Mask
| #define GPIO_INTSRC_INTSRC6_Pos (6) |
GPIO_T::INTSRC: INTSRC6 Position
| #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
GPIO_T::INTSRC: INTSRC7 Mask
| #define GPIO_INTSRC_INTSRC7_Pos (7) |
GPIO_T::INTSRC: INTSRC7 Position
| #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
GPIO_T::INTSRC: INTSRC8 Mask
| #define GPIO_INTSRC_INTSRC8_Pos (8) |
GPIO_T::INTSRC: INTSRC8 Position
| #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
GPIO_T::INTSRC: INTSRC9 Mask
| #define GPIO_INTSRC_INTSRC9_Pos (9) |
GPIO_T::INTSRC: INTSRC9 Position
| #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
GPIO_T::INTTYPE: TYPE0 Mask
| #define GPIO_INTTYPE_TYPE0_Pos (0) |
GPIO_T::INTTYPE: TYPE0 Position
| #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
GPIO_T::INTTYPE: TYPE10 Mask
| #define GPIO_INTTYPE_TYPE10_Pos (10) |
GPIO_T::INTTYPE: TYPE10 Position
| #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
GPIO_T::INTTYPE: TYPE11 Mask
| #define GPIO_INTTYPE_TYPE11_Pos (11) |
GPIO_T::INTTYPE: TYPE11 Position
| #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
GPIO_T::INTTYPE: TYPE12 Mask
| #define GPIO_INTTYPE_TYPE12_Pos (12) |
GPIO_T::INTTYPE: TYPE12 Position
| #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
GPIO_T::INTTYPE: TYPE13 Mask
| #define GPIO_INTTYPE_TYPE13_Pos (13) |
GPIO_T::INTTYPE: TYPE13 Position
| #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
GPIO_T::INTTYPE: TYPE14 Mask
| #define GPIO_INTTYPE_TYPE14_Pos (14) |
GPIO_T::INTTYPE: TYPE14 Position
| #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
GPIO_T::INTTYPE: TYPE15 Mask
| #define GPIO_INTTYPE_TYPE15_Pos (15) |
GPIO_T::INTTYPE: TYPE15 Position
| #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
GPIO_T::INTTYPE: TYPE1 Mask
| #define GPIO_INTTYPE_TYPE1_Pos (1) |
GPIO_T::INTTYPE: TYPE1 Position
| #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
GPIO_T::INTTYPE: TYPE2 Mask
| #define GPIO_INTTYPE_TYPE2_Pos (2) |
GPIO_T::INTTYPE: TYPE2 Position
| #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
GPIO_T::INTTYPE: TYPE3 Mask
| #define GPIO_INTTYPE_TYPE3_Pos (3) |
GPIO_T::INTTYPE: TYPE3 Position
| #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
GPIO_T::INTTYPE: TYPE4 Mask
| #define GPIO_INTTYPE_TYPE4_Pos (4) |
GPIO_T::INTTYPE: TYPE4 Position
| #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
GPIO_T::INTTYPE: TYPE5 Mask
| #define GPIO_INTTYPE_TYPE5_Pos (5) |
GPIO_T::INTTYPE: TYPE5 Position
| #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
GPIO_T::INTTYPE: TYPE6 Mask
| #define GPIO_INTTYPE_TYPE6_Pos (6) |
GPIO_T::INTTYPE: TYPE6 Position
| #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
GPIO_T::INTTYPE: TYPE7 Mask
| #define GPIO_INTTYPE_TYPE7_Pos (7) |
GPIO_T::INTTYPE: TYPE7 Position
| #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
GPIO_T::INTTYPE: TYPE8 Mask
| #define GPIO_INTTYPE_TYPE8_Pos (8) |
GPIO_T::INTTYPE: TYPE8 Position
| #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
GPIO_T::INTTYPE: TYPE9 Mask
| #define GPIO_INTTYPE_TYPE9_Pos (9) |
GPIO_T::INTTYPE: TYPE9 Position
| #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
GPIO_T::MODE: MODE0 Mask
| #define GPIO_MODE_MODE0_Pos (0) |
@addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller
GPIO_T::MODE: MODE0 Position
| #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
GPIO_T::MODE: MODE10 Mask
| #define GPIO_MODE_MODE10_Pos (20) |
GPIO_T::MODE: MODE10 Position
| #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
GPIO_T::MODE: MODE11 Mask
| #define GPIO_MODE_MODE11_Pos (22) |
GPIO_T::MODE: MODE11 Position
| #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
GPIO_T::MODE: MODE12 Mask
| #define GPIO_MODE_MODE12_Pos (24) |
GPIO_T::MODE: MODE12 Position
| #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
GPIO_T::MODE: MODE13 Mask
| #define GPIO_MODE_MODE13_Pos (26) |
GPIO_T::MODE: MODE13 Position
| #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
GPIO_T::MODE: MODE14 Mask
| #define GPIO_MODE_MODE14_Pos (28) |
GPIO_T::MODE: MODE14 Position
| #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
GPIO_T::MODE: MODE15 Mask
| #define GPIO_MODE_MODE15_Pos (30) |
GPIO_T::MODE: MODE15 Position
| #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
GPIO_T::MODE: MODE1 Mask
| #define GPIO_MODE_MODE1_Pos (2) |
GPIO_T::MODE: MODE1 Position
| #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
GPIO_T::MODE: MODE2 Mask
| #define GPIO_MODE_MODE2_Pos (4) |
GPIO_T::MODE: MODE2 Position
| #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
GPIO_T::MODE: MODE3 Mask
| #define GPIO_MODE_MODE3_Pos (6) |
GPIO_T::MODE: MODE3 Position
| #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
GPIO_T::MODE: MODE4 Mask
| #define GPIO_MODE_MODE4_Pos (8) |
GPIO_T::MODE: MODE4 Position
| #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
GPIO_T::MODE: MODE5 Mask
| #define GPIO_MODE_MODE5_Pos (10) |
GPIO_T::MODE: MODE5 Position
| #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
GPIO_T::MODE: MODE6 Mask
| #define GPIO_MODE_MODE6_Pos (12) |
GPIO_T::MODE: MODE6 Position
| #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
GPIO_T::MODE: MODE7 Mask
| #define GPIO_MODE_MODE7_Pos (14) |
GPIO_T::MODE: MODE7 Position
| #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
GPIO_T::MODE: MODE8 Mask
| #define GPIO_MODE_MODE8_Pos (16) |
GPIO_T::MODE: MODE8 Position
| #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
GPIO_T::MODE: MODE9 Mask
| #define GPIO_MODE_MODE9_Pos (18) |
GPIO_T::MODE: MODE9 Position
| #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
GPIO_T::PIN: PIN0 Mask
| #define GPIO_PIN_PIN0_Pos (0) |
GPIO_T::PIN: PIN0 Position
| #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
GPIO_T::PIN: PIN10 Mask
| #define GPIO_PIN_PIN10_Pos (10) |
GPIO_T::PIN: PIN10 Position
| #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
GPIO_T::PIN: PIN11 Mask
| #define GPIO_PIN_PIN11_Pos (11) |
GPIO_T::PIN: PIN11 Position
| #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
GPIO_T::PIN: PIN12 Mask
| #define GPIO_PIN_PIN12_Pos (12) |
GPIO_T::PIN: PIN12 Position
| #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
GPIO_T::PIN: PIN13 Mask
| #define GPIO_PIN_PIN13_Pos (13) |
GPIO_T::PIN: PIN13 Position
| #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
GPIO_T::PIN: PIN14 Mask
| #define GPIO_PIN_PIN14_Pos (14) |
GPIO_T::PIN: PIN14 Position
| #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
GPIO_T::PIN: PIN15 Mask
| #define GPIO_PIN_PIN15_Pos (15) |
GPIO_T::PIN: PIN15 Position
| #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
GPIO_T::PIN: PIN1 Mask
| #define GPIO_PIN_PIN1_Pos (1) |
GPIO_T::PIN: PIN1 Position
| #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
GPIO_T::PIN: PIN2 Mask
| #define GPIO_PIN_PIN2_Pos (2) |
GPIO_T::PIN: PIN2 Position
| #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
GPIO_T::PIN: PIN3 Mask
| #define GPIO_PIN_PIN3_Pos (3) |
GPIO_T::PIN: PIN3 Position
| #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
GPIO_T::PIN: PIN4 Mask
| #define GPIO_PIN_PIN4_Pos (4) |
GPIO_T::PIN: PIN4 Position
| #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
GPIO_T::PIN: PIN5 Mask
| #define GPIO_PIN_PIN5_Pos (5) |
GPIO_T::PIN: PIN5 Position
| #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
GPIO_T::PIN: PIN6 Mask
| #define GPIO_PIN_PIN6_Pos (6) |
GPIO_T::PIN: PIN6 Position
| #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
GPIO_T::PIN: PIN7 Mask
| #define GPIO_PIN_PIN7_Pos (7) |
GPIO_T::PIN: PIN7 Position
| #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
GPIO_T::PIN: PIN8 Mask
| #define GPIO_PIN_PIN8_Pos (8) |
GPIO_T::PIN: PIN8 Position
| #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
GPIO_T::PIN: PIN9 Mask
| #define GPIO_PIN_PIN9_Pos (9) |
GPIO_T::PIN: PIN9 Position
| #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) |
GPIO_T::SLEWCTL: HSREN0 Mask
| #define GPIO_SLEWCTL_HSREN0_Pos (0) |
GPIO_T::SLEWCTL: HSREN0 Position
| #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) |
GPIO_T::SLEWCTL: HSREN10 Mask
| #define GPIO_SLEWCTL_HSREN10_Pos (10) |
GPIO_T::SLEWCTL: HSREN10 Position
| #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) |
GPIO_T::SLEWCTL: HSREN11 Mask
| #define GPIO_SLEWCTL_HSREN11_Pos (11) |
GPIO_T::SLEWCTL: HSREN11 Position
| #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) |
GPIO_T::SLEWCTL: HSREN12 Mask
| #define GPIO_SLEWCTL_HSREN12_Pos (12) |
GPIO_T::SLEWCTL: HSREN12 Position
| #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) |
GPIO_T::SLEWCTL: HSREN13 Mask
| #define GPIO_SLEWCTL_HSREN13_Pos (13) |
GPIO_T::SLEWCTL: HSREN13 Position
| #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) |
GPIO_T::SLEWCTL: HSREN14 Mask
| #define GPIO_SLEWCTL_HSREN14_Pos (14) |
GPIO_T::SLEWCTL: HSREN14 Position
| #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) |
GPIO_T::SLEWCTL: HSREN15 Mask
| #define GPIO_SLEWCTL_HSREN15_Pos (15) |
GPIO_T::SLEWCTL: HSREN15 Position
| #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) |
GPIO_T::SLEWCTL: HSREN1 Mask
| #define GPIO_SLEWCTL_HSREN1_Pos (1) |
GPIO_T::SLEWCTL: HSREN1 Position
| #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) |
GPIO_T::SLEWCTL: HSREN2 Mask
| #define GPIO_SLEWCTL_HSREN2_Pos (2) |
GPIO_T::SLEWCTL: HSREN2 Position
| #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) |
GPIO_T::SLEWCTL: HSREN3 Mask
| #define GPIO_SLEWCTL_HSREN3_Pos (3) |
GPIO_T::SLEWCTL: HSREN3 Position
| #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) |
GPIO_T::SLEWCTL: HSREN4 Mask
| #define GPIO_SLEWCTL_HSREN4_Pos (4) |
GPIO_T::SLEWCTL: HSREN4 Position
| #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) |
GPIO_T::SLEWCTL: HSREN5 Mask
| #define GPIO_SLEWCTL_HSREN5_Pos (5) |
GPIO_T::SLEWCTL: HSREN5 Position
| #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) |
GPIO_T::SLEWCTL: HSREN6 Mask
| #define GPIO_SLEWCTL_HSREN6_Pos (6) |
GPIO_T::SLEWCTL: HSREN6 Position
| #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) |
GPIO_T::SLEWCTL: HSREN7 Mask
| #define GPIO_SLEWCTL_HSREN7_Pos (7) |
GPIO_T::SLEWCTL: HSREN7 Position
| #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) |
GPIO_T::SLEWCTL: HSREN8 Mask
| #define GPIO_SLEWCTL_HSREN8_Pos (8) |
GPIO_T::SLEWCTL: HSREN8 Position
| #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) |
GPIO_T::SLEWCTL: HSREN9 Mask
| #define GPIO_SLEWCTL_HSREN9_Pos (9) |
GPIO_T::SLEWCTL: HSREN9 Position
| #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) |
GPIO_T::SMTEN: SMTEN0 Mask
| #define GPIO_SMTEN_SMTEN0_Pos (0) |
GPIO_T::SMTEN: SMTEN0 Position
| #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) |
GPIO_T::SMTEN: SMTEN10 Mask
| #define GPIO_SMTEN_SMTEN10_Pos (10) |
GPIO_T::SMTEN: SMTEN10 Position
| #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) |
GPIO_T::SMTEN: SMTEN11 Mask
| #define GPIO_SMTEN_SMTEN11_Pos (11) |
GPIO_T::SMTEN: SMTEN11 Position
| #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) |
GPIO_T::SMTEN: SMTEN12 Mask
| #define GPIO_SMTEN_SMTEN12_Pos (12) |
GPIO_T::SMTEN: SMTEN12 Position
| #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) |
GPIO_T::SMTEN: SMTEN13 Mask
| #define GPIO_SMTEN_SMTEN13_Pos (13) |
GPIO_T::SMTEN: SMTEN13 Position
| #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) |
GPIO_T::SMTEN: SMTEN14 Mask
| #define GPIO_SMTEN_SMTEN14_Pos (14) |
GPIO_T::SMTEN: SMTEN14 Position
| #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) |
GPIO_T::SMTEN: SMTEN15 Mask
| #define GPIO_SMTEN_SMTEN15_Pos (15) |
GPIO_T::SMTEN: SMTEN15 Position
| #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) |
GPIO_T::SMTEN: SMTEN1 Mask
| #define GPIO_SMTEN_SMTEN1_Pos (1) |
GPIO_T::SMTEN: SMTEN1 Position
| #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) |
GPIO_T::SMTEN: SMTEN2 Mask
| #define GPIO_SMTEN_SMTEN2_Pos (2) |
GPIO_T::SMTEN: SMTEN2 Position
| #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) |
GPIO_T::SMTEN: SMTEN3 Mask
| #define GPIO_SMTEN_SMTEN3_Pos (3) |
GPIO_T::SMTEN: SMTEN3 Position
| #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) |
GPIO_T::SMTEN: SMTEN4 Mask
| #define GPIO_SMTEN_SMTEN4_Pos (4) |
GPIO_T::SMTEN: SMTEN4 Position
| #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) |
GPIO_T::SMTEN: SMTEN5 Mask
| #define GPIO_SMTEN_SMTEN5_Pos (5) |
GPIO_T::SMTEN: SMTEN5 Position
| #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) |
GPIO_T::SMTEN: SMTEN6 Mask
| #define GPIO_SMTEN_SMTEN6_Pos (6) |
GPIO_T::SMTEN: SMTEN6 Position
| #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) |
GPIO_T::SMTEN: SMTEN7 Mask
| #define GPIO_SMTEN_SMTEN7_Pos (7) |
GPIO_T::SMTEN: SMTEN7 Position
| #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) |
GPIO_T::SMTEN: SMTEN8 Mask
| #define GPIO_SMTEN_SMTEN8_Pos (8) |
GPIO_T::SMTEN: SMTEN8 Position
| #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) |
GPIO_T::SMTEN: SMTEN9 Mask
| #define GPIO_SMTEN_SMTEN9_Pos (9) |
GPIO_T::SMTEN: SMTEN9 Position
| #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) |
I2C_T::ADDR0: ADDR Mask
| #define I2C_ADDR0_ADDR_Pos (1) |
I2C_T::ADDR0: ADDR Position
| #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
I2C_T::ADDR0: GC Mask
| #define I2C_ADDR0_GC_Pos (0) |
I2C_T::ADDR0: GC Position
| #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) |
I2C_T::ADDR1: ADDR Mask
| #define I2C_ADDR1_ADDR_Pos (1) |
I2C_T::ADDR1: ADDR Position
| #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
I2C_T::ADDR1: GC Mask
| #define I2C_ADDR1_GC_Pos (0) |
I2C_T::ADDR1: GC Position
| #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) |
I2C_T::ADDR2: ADDR Mask
| #define I2C_ADDR2_ADDR_Pos (1) |
I2C_T::ADDR2: ADDR Position
| #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) |
I2C_T::ADDR2: GC Mask
| #define I2C_ADDR2_GC_Pos (0) |
I2C_T::ADDR2: GC Position
| #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) |
I2C_T::ADDR3: ADDR Mask
| #define I2C_ADDR3_ADDR_Pos (1) |
I2C_T::ADDR3: ADDR Position
| #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) |
I2C_T::ADDR3: GC Mask
| #define I2C_ADDR3_GC_Pos (0) |
I2C_T::ADDR3: GC Position
| #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) |
I2C_T::ADDRMSK0: ADDRMSK Mask
| #define I2C_ADDRMSK0_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK0: ADDRMSK Position
| #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) |
I2C_T::ADDRMSK1: ADDRMSK Mask
| #define I2C_ADDRMSK1_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK1: ADDRMSK Position
| #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) |
I2C_T::ADDRMSK2: ADDRMSK Mask
| #define I2C_ADDRMSK2_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK2: ADDRMSK Position
| #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) |
I2C_T::ADDRMSK3: ADDRMSK Mask
| #define I2C_ADDRMSK3_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK3: ADDRMSK Position
| #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) |
I2C_T::BUSCTL: ACKM9SI Mask
| #define I2C_BUSCTL_ACKM9SI_Pos (11) |
I2C_T::BUSCTL: ACKM9SI Position
| #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) |
I2C_T::BUSCTL: ACKMEN Mask
| #define I2C_BUSCTL_ACKMEN_Pos (0) |
I2C_T::BUSCTL: ACKMEN Position
| #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) |
I2C_T::BUSCTL: ALERTEN Mask
| #define I2C_BUSCTL_ALERTEN_Pos (4) |
I2C_T::BUSCTL: ALERTEN Position
| #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) |
I2C_T::BUSCTL: BMDEN Mask
| #define I2C_BUSCTL_BMDEN_Pos (2) |
I2C_T::BUSCTL: BMDEN Position
| #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) |
I2C_T::BUSCTL: BMHEN Mask
| #define I2C_BUSCTL_BMHEN_Pos (3) |
I2C_T::BUSCTL: BMHEN Position
| #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) |
I2C_T::BUSCTL: BUSEN Mask
| #define I2C_BUSCTL_BUSEN_Pos (7) |
I2C_T::BUSCTL: BUSEN Position
| #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) |
I2C_T::BUSCTL: PECCLR Mask
| #define I2C_BUSCTL_PECCLR_Pos (10) |
I2C_T::BUSCTL: PECCLR Position
| #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) |
I2C_T::BUSCTL: PECEN Mask
| #define I2C_BUSCTL_PECEN_Pos (1) |
I2C_T::BUSCTL: PECEN Position
| #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) |
I2C_T::BUSCTL: PECTXEN Mask
| #define I2C_BUSCTL_PECTXEN_Pos (8) |
I2C_T::BUSCTL: PECTXEN Position
| #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) |
I2C_T::BUSCTL: SCTLOEN Mask
| #define I2C_BUSCTL_SCTLOEN_Pos (6) |
I2C_T::BUSCTL: SCTLOEN Position
| #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) |
I2C_T::BUSCTL: SCTLOSTS Mask
| #define I2C_BUSCTL_SCTLOSTS_Pos (5) |
I2C_T::BUSCTL: SCTLOSTS Position
| #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) |
I2C_T::BUSCTL: TIDLE Mask
| #define I2C_BUSCTL_TIDLE_Pos (9) |
I2C_T::BUSCTL: TIDLE Position
| #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) |
I2C_T::BUSSTS: ALERT Mask
| #define I2C_BUSSTS_ALERT_Pos (3) |
I2C_T::BUSSTS: ALERT Position
| #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) |
I2C_T::BUSSTS: BCDONE Mask
| #define I2C_BUSSTS_BCDONE_Pos (1) |
I2C_T::BUSSTS: BCDONE Position
| #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) |
I2C_T::BUSSTS: BUSTO Mask
| #define I2C_BUSSTS_BUSTO_Pos (5) |
I2C_T::BUSSTS: BUSTO Position
| #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) |
I2C_T::BUSSTS: BUSY Mask
| #define I2C_BUSSTS_BUSY_Pos (0) |
I2C_T::BUSSTS: BUSY Position
| #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) |
I2C_T::BUSSTS: CLKTO Mask
| #define I2C_BUSSTS_CLKTO_Pos (6) |
I2C_T::BUSSTS: CLKTO Position
| #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) |
I2C_T::BUSSTS: PECERR Mask
| #define I2C_BUSSTS_PECERR_Pos (2) |
I2C_T::BUSSTS: PECERR Position
| #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) |
I2C_T::BUSSTS: SCTLDIN Mask
| #define I2C_BUSSTS_SCTLDIN_Pos (4) |
I2C_T::BUSSTS: SCTLDIN Position
| #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) |
I2C_T::BUSTCTL: BUSTOEN Mask
| #define I2C_BUSTCTL_BUSTOEN_Pos (0) |
I2C_T::BUSTCTL: BUSTOEN Position
| #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) |
I2C_T::BUSTCTL: BUSTOIEN Mask
| #define I2C_BUSTCTL_BUSTOIEN_Pos (2) |
I2C_T::BUSTCTL: BUSTOIEN Position
| #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) |
I2C_T::BUSTCTL: CLKTOEN Mask
| #define I2C_BUSTCTL_CLKTOEN_Pos (1) |
I2C_T::BUSTCTL: CLKTOEN Position
| #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) |
I2C_T::BUSTCTL: CLKTOIEN Mask
| #define I2C_BUSTCTL_CLKTOIEN_Pos (3) |
I2C_T::BUSTCTL: CLKTOIEN Position
| #define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) |
I2C_T::BUSTCTL: PECIEN Mask
| #define I2C_BUSTCTL_PECIEN_Pos (5) |
I2C_T::BUSTCTL: PECIEN Position
| #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) |
I2C_T::BUSTCTL: TORSTEN Mask
| #define I2C_BUSTCTL_TORSTEN_Pos (4) |
I2C_T::BUSTCTL: TORSTEN Position
| #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) |
I2C_T::BUSTOUT: BUSTO Mask
| #define I2C_BUSTOUT_BUSTO_Pos (0) |
I2C_T::BUSTOUT: BUSTO Position
| #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) |
I2C_T::CLKDIV: DIVIDER Mask
| #define I2C_CLKDIV_DIVIDER_Pos (0) |
I2C_T::CLKDIV: DIVIDER Position
| #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) |
I2C_T::CLKTOUT: CLKTO Mask
| #define I2C_CLKTOUT_CLKTO_Pos (0) |
I2C_T::CLKTOUT: CLKTO Position
| #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) |
I2C_T::CTL: AA Mask
| #define I2C_CTL_AA_Pos (2) |
@addtogroup I2C_CONST I2C Bit Field Definition Constant Definitions for I2C Controller
I2C_T::CTL: AA Position
| #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) |
I2C_T::CTL: I2CEN Mask
| #define I2C_CTL_I2CEN_Pos (6) |
I2C_T::CTL: I2CEN Position
| #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) |
I2C_T::CTL: INTEN Mask
| #define I2C_CTL_INTEN_Pos (7) |
I2C_T::CTL: INTEN Position
| #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) |
I2C_T::CTL: SI Mask
| #define I2C_CTL_SI_Pos (3) |
I2C_T::CTL: SI Position
| #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) |
I2C_T::CTL: STA Mask
| #define I2C_CTL_STA_Pos (5) |
I2C_T::CTL: STA Position
| #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) |
I2C_T::CTL: STO Mask
| #define I2C_CTL_STO_Pos (4) |
I2C_T::CTL: STO Position
| #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
I2C_T::DAT: DAT Mask
| #define I2C_DAT_DAT_Pos (0) |
I2C_T::DAT: DAT Position
| #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) |
I2C_T::PKTCRC: PECCRC Mask
| #define I2C_PKTCRC_PECCRC_Pos (0) |
I2C_T::PKTCRC: PECCRC Position
| #define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) |
I2C_T::PKTSIZE: PLDSIZE Mask
| #define I2C_PKTSIZE_PLDSIZE_Pos (0) |
I2C_T::PKTSIZE: PLDSIZE Position
| #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
I2C_T::STATUS: STATUS Mask
| #define I2C_STATUS_STATUS_Pos (0) |
I2C_T::STATUS: STATUS Position
| #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
I2C_T::TOCTL: TOCDIV4 Mask
| #define I2C_TOCTL_TOCDIV4_Pos (1) |
I2C_T::TOCTL: TOCDIV4 Position
| #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
I2C_T::TOCTL: TOCEN Mask
| #define I2C_TOCTL_TOCEN_Pos (2) |
I2C_T::TOCTL: TOCEN Position
| #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) |
I2C_T::TOCTL: TOIF Mask
| #define I2C_TOCTL_TOIF_Pos (0) |
I2C_T::TOCTL: TOIF Position
| #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) |
I2C_T::WKCTL: WKEN Mask
| #define I2C_WKCTL_WKEN_Pos (0) |
I2C_T::WKCTL: WKEN Position
| #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) |
I2C_T::WKSTS: WKIF Mask
| #define I2C_WKSTS_WKIF_Pos (0) |
I2C_T::WKSTS: WKIF Position
| #define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) |
PDMA_T::ABTSTS: ABTIFn Mask
| #define PDMA_ABTSTS_ABTIFn_Pos (0) |
PDMA_T::ABTSTS: ABTIFn Position
| #define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) |
PDMA_T::CHCTL: CHENn Mask
| #define PDMA_CHCTL_CHENn_Pos (0) |
PDMA_T::CHCTL: CHENn Position
| #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) |
PDMA_T::CURSCAT: CURADDR Mask
| #define PDMA_CURSCAT_CURADDR_Pos (0) |
PDMA_T::CURSCAT: CURADDR Position
| #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) |
DSCT_T::CTL: BURSIZE Mask
| #define PDMA_DSCT_CTL_BURSIZE_Pos (4) |
DSCT_T::CTL: BURSIZE Position
| #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) |
DSCT_T::CTL: DAINC Mask
| #define PDMA_DSCT_CTL_DAINC_Pos (10) |
DSCT_T::CTL: DAINC Position
| #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) |
DSCT_T::CTL: OPMODE Mask
| #define PDMA_DSCT_CTL_OPMODE_Pos (0) |
@addtogroup PDMA_CONST PDMA Bit Field Definition Constant Definitions for PDMA Controller
DSCT_T::CTL: OPMODE Position
| #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) |
DSCT_T::CTL: SAINC Mask
| #define PDMA_DSCT_CTL_SAINC_Pos (8) |
DSCT_T::CTL: SAINC Position
| #define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) |
DSCT_T::CTL: TBINTDIS Mask
| #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) |
DSCT_T::CTL: TBINTDIS Position
| #define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) |
DSCT_T::CTL: TXCNT Mask
| #define PDMA_DSCT_CTL_TXCNT_Pos (16) |
DSCT_T::CTL: TXCNT Position
| #define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) |
DSCT_T::CTL: TXTYPE Mask
| #define PDMA_DSCT_CTL_TXTYPE_Pos (2) |
DSCT_T::CTL: TXTYPE Position
| #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) |
DSCT_T::CTL: TXWIDTH Mask
| #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) |
DSCT_T::CTL: TXWIDTH Position
| #define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) |
DSCT_T::DA: DA Mask
| #define PDMA_DSCT_DA_DA_Pos (0) |
DSCT_T::DA: DA Position
| #define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) |
DSCT_T::NEXT: NEXT Mask
| #define PDMA_DSCT_NEXT_NEXT_Pos (0) |
DSCT_T::NEXT: NEXT Position
| #define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) |
DSCT_T::SA: SA Mask
| #define PDMA_DSCT_SA_SA_Pos (0) |
DSCT_T::SA: SA Position
| #define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) |
PDMA_T::INTEN: INTENn Mask
| #define PDMA_INTEN_INTENn_Pos (0) |
PDMA_T::INTEN: INTENn Position
| #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) |
PDMA_T::INTSTS: ABTIF Mask
| #define PDMA_INTSTS_ABTIF_Pos (0) |
PDMA_T::INTSTS: ABTIF Position
| #define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) |
PDMA_T::INTSTS: REQTOFn Mask
| #define PDMA_INTSTS_REQTOFn_Pos (8) |
PDMA_T::INTSTS: REQTOFn Position
| #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) |
PDMA_T::INTSTS: TDIF Mask
| #define PDMA_INTSTS_TDIF_Pos (1) |
PDMA_T::INTSTS: TDIF Position
| #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) |
PDMA_T::INTSTS: TEIF Mask
| #define PDMA_INTSTS_TEIF_Pos (2) |
PDMA_T::INTSTS: TEIF Position
| #define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) |
PDMA_T::PRICLR: FPRICLRn Mask
| #define PDMA_PRICLR_FPRICLRn_Pos (0) |
PDMA_T::PRICLR: FPRICLRn Position
| #define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) |
PDMA_T::PRISET: FPRISETn Mask
| #define PDMA_PRISET_FPRISETn_Pos (0) |
PDMA_T::PRISET: FPRISETn Position
| #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) |
PDMA_T::REQSEL0_3: REQSRC0 Mask
| #define PDMA_REQSEL0_3_REQSRC0_Pos (0) |
PDMA_T::REQSEL0_3: REQSRC0 Position
| #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) |
PDMA_T::REQSEL0_3: REQSRC1 Mask
| #define PDMA_REQSEL0_3_REQSRC1_Pos (8) |
PDMA_T::REQSEL0_3: REQSRC1 Position
| #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) |
PDMA_T::REQSEL0_3: REQSRC2 Mask
| #define PDMA_REQSEL0_3_REQSRC2_Pos (16) |
PDMA_T::REQSEL0_3: REQSRC2 Position
| #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) |
PDMA_T::REQSEL0_3: REQSRC3 Mask
| #define PDMA_REQSEL0_3_REQSRC3_Pos (24) |
PDMA_T::REQSEL0_3: REQSRC3 Position
| #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) |
PDMA_T::REQSEL4_7: REQSRC4 Mask
| #define PDMA_REQSEL4_7_REQSRC4_Pos (0) |
PDMA_T::REQSEL4_7: REQSRC4 Position
| #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) |
PDMA_T::REQSEL4_7: REQSRC5 Mask
| #define PDMA_REQSEL4_7_REQSRC5_Pos (8) |
PDMA_T::REQSEL4_7: REQSRC5 Position
| #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) |
PDMA_T::REQSEL4_7: REQSRC6 Mask
| #define PDMA_REQSEL4_7_REQSRC6_Pos (16) |
PDMA_T::REQSEL4_7: REQSRC6 Position
| #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) |
PDMA_T::REQSEL4_7: REQSRC7 Mask
| #define PDMA_REQSEL4_7_REQSRC7_Pos (24) |
PDMA_T::REQSEL4_7: REQSRC7 Position
| #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) |
PDMA_T::REQSEL8_11: REQSRC10 Mask
| #define PDMA_REQSEL8_11_REQSRC10_Pos (16) |
PDMA_T::REQSEL8_11: REQSRC10 Position
| #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) |
PDMA_T::REQSEL8_11: REQSRC11 Mask
| #define PDMA_REQSEL8_11_REQSRC11_Pos (24) |
PDMA_T::REQSEL8_11: REQSRC11 Position
| #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) |
PDMA_T::REQSEL8_11: REQSRC8 Mask
| #define PDMA_REQSEL8_11_REQSRC8_Pos (0) |
PDMA_T::REQSEL8_11: REQSRC8 Position
| #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) |
PDMA_T::REQSEL8_11: REQSRC9 Mask
| #define PDMA_REQSEL8_11_REQSRC9_Pos (8) |
PDMA_T::REQSEL8_11: REQSRC9 Position
| #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) |
PDMA_T::SCATBA: SCATBA Mask
| #define PDMA_SCATBA_SCATBA_Pos (16) |
PDMA_T::SCATBA: SCATBA Position
| #define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) |
PDMA_T::SCATSTS: TEMPTYFn Mask
| #define PDMA_SCATSTS_TEMPTYFn_Pos (0) |
PDMA_T::SCATSTS: TEMPTYFn Position
| #define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) |
PDMA_T::STOP: STOPn Mask
| #define PDMA_STOP_STOPn_Pos (0) |
PDMA_T::STOP: STOPn Position
| #define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) |
PDMA_T::SWREQ: SWREQn Mask
| #define PDMA_SWREQ_SWREQn_Pos (0) |
PDMA_T::SWREQ: SWREQn Position
| #define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) |
PDMA_T::TACTSTS: TXACTFn Mask
| #define PDMA_TACTSTS_TXACTFn_Pos (0) |
PDMA_T::TACTSTS: TXACTFn Position
| #define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) |
PDMA_T::TDSTS: TDIFn Mask
| #define PDMA_TDSTS_TDIFn_Pos (0) |
PDMA_T::TDSTS: TDIFn Position
| #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) |
PDMA_T::TOC0_1: TOC0 Mask
| #define PDMA_TOC0_1_TOC0_Pos (0) |
PDMA_T::TOC0_1: TOC0 Position
| #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) |
PDMA_T::TOC0_1: TOC1 Mask
| #define PDMA_TOC0_1_TOC1_Pos (16) |
PDMA_T::TOC0_1: TOC1 Position
| #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) |
PDMA_T::TOC2_3: TOC2 Mask
| #define PDMA_TOC2_3_TOC2_Pos (0) |
PDMA_T::TOC2_3: TOC2 Position
| #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) |
PDMA_T::TOC2_3: TOC3 Mask
| #define PDMA_TOC2_3_TOC3_Pos (16) |
PDMA_T::TOC2_3: TOC3 Position
| #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) |
PDMA_T::TOC4_5: TOC4 Mask
| #define PDMA_TOC4_5_TOC4_Pos (0) |
PDMA_T::TOC4_5: TOC4 Position
| #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) |
PDMA_T::TOC4_5: TOC5 Mask
| #define PDMA_TOC4_5_TOC5_Pos (16) |
PDMA_T::TOC4_5: TOC5 Position
| #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) |
PDMA_T::TOC6_7: TOC6 Mask
| #define PDMA_TOC6_7_TOC6_Pos (0) |
PDMA_T::TOC6_7: TOC6 Position
| #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) |
PDMA_T::TOC6_7: TOC7 Mask
| #define PDMA_TOC6_7_TOC7_Pos (16) |
PDMA_T::TOC6_7: TOC7 Position
| #define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) |
PDMA_T::TOUTEN: TOUTENn Mask
| #define PDMA_TOUTEN_TOUTENn_Pos (0) |
PDMA_T::TOUTEN: TOUTENn Position
| #define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) |
PDMA_T::TOUTIEN: TOUTIENn Mask
| #define PDMA_TOUTIEN_TOUTIENn_Pos (0) |
PDMA_T::TOUTIEN: TOUTIENn Position
| #define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) |
PDMA_T::TRGSTS: REQSTSn Mask
| #define PDMA_TRGSTS_REQSTSn_Pos (0) |
PDMA_T::TRGSTS: REQSTSn Position
| #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) |
PWM_T::BNF: BK0SRC Mask
| #define PWM_BNF_BK0SRC_Pos (16) |
PWM_T::BNF: BK0SRC Position
| #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) |
PWM_T::BNF: BK1SRC Mask
| #define PWM_BNF_BK1SRC_Pos (24) |
PWM_T::BNF: BK1SRC Position
| #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) |
PWM_T::BNF: BRK0FCNT Mask
| #define PWM_BNF_BRK0FCNT_Pos (4) |
PWM_T::BNF: BRK0FCNT Position
| #define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) |
PWM_T::BNF: BRK0NFEN Mask
| #define PWM_BNF_BRK0NFEN_Pos (0) |
PWM_T::BNF: BRK0NFEN Position
| #define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) |
PWM_T::BNF: BRK0NFSEL Mask
| #define PWM_BNF_BRK0NFSEL_Pos (1) |
PWM_T::BNF: BRK0NFSEL Position
| #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) |
PWM_T::BNF: BRK0PINV Mask
| #define PWM_BNF_BRK0PINV_Pos (7) |
PWM_T::BNF: BRK0PINV Position
| #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) |
PWM_T::BNF: BRK1FCNT Mask
| #define PWM_BNF_BRK1FCNT_Pos (12) |
PWM_T::BNF: BRK1FCNT Position
| #define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) |
PWM_T::BNF: BRK1NFEN Mask
| #define PWM_BNF_BRK1NFEN_Pos (8) |
PWM_T::BNF: BRK1NFEN Position
| #define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) |
PWM_T::BNF: BRK1NFSEL Mask
| #define PWM_BNF_BRK1NFSEL_Pos (9) |
PWM_T::BNF: BRK1NFSEL Position
| #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) |
PWM_T::BNF: BRK1PINV Mask
| #define PWM_BNF_BRK1PINV_Pos (15) |
PWM_T::BNF: BRK1PINV Position
| #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) |
PWM_T::BRKCTL0_1: BRKAEVEN Mask
| #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL0_1: BRKAEVEN Position
| #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) |
PWM_T::BRKCTL0_1: BRKAODD Mask
| #define PWM_BRKCTL0_1_BRKAODD_Pos (18) |
PWM_T::BRKCTL0_1: BRKAODD Position
| #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) |
PWM_T::BRKCTL0_1: BRKP0EEN Mask
| #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL0_1: BRKP0EEN Position
| #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) |
PWM_T::BRKCTL0_1: BRKP0LEN Mask
| #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL0_1: BRKP0LEN Position
| #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) |
PWM_T::BRKCTL0_1: BRKP1EEN Mask
| #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL0_1: BRKP1EEN Position
| #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) |
PWM_T::BRKCTL0_1: BRKP1LEN Mask
| #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL0_1: BRKP1LEN Position
| #define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) |
PWM_T::BRKCTL0_1: SYSEBEN Mask
| #define PWM_BRKCTL0_1_SYSEBEN_Pos (7) |
PWM_T::BRKCTL0_1: SYSEBEN Position
| #define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) |
PWM_T::BRKCTL0_1: SYSLBEN Mask
| #define PWM_BRKCTL0_1_SYSLBEN_Pos (15) |
PWM_T::BRKCTL0_1: SYSLBEN Position
| #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) |
PWM_T::BRKCTL2_3: BRKAEVEN Mask
| #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL2_3: BRKAEVEN Position
| #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) |
PWM_T::BRKCTL2_3: BRKAODD Mask
| #define PWM_BRKCTL2_3_BRKAODD_Pos (18) |
PWM_T::BRKCTL2_3: BRKAODD Position
| #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) |
PWM_T::BRKCTL2_3: BRKP0EEN Mask
| #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL2_3: BRKP0EEN Position
| #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) |
PWM_T::BRKCTL2_3: BRKP0LEN Mask
| #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL2_3: BRKP0LEN Position
| #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) |
PWM_T::BRKCTL2_3: BRKP1EEN Mask
| #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL2_3: BRKP1EEN Position
| #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) |
PWM_T::BRKCTL2_3: BRKP1LEN Mask
| #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL2_3: BRKP1LEN Position
| #define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) |
PWM_T::BRKCTL2_3: SYSEBEN Mask
| #define PWM_BRKCTL2_3_SYSEBEN_Pos (7) |
PWM_T::BRKCTL2_3: SYSEBEN Position
| #define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) |
PWM_T::BRKCTL2_3: SYSLBEN Mask
| #define PWM_BRKCTL2_3_SYSLBEN_Pos (15) |
PWM_T::BRKCTL2_3: SYSLBEN Position
| #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) |
PWM_T::BRKCTL4_5: BRKAEVEN Mask
| #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL4_5: BRKAEVEN Position
| #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) |
PWM_T::BRKCTL4_5: BRKAODD Mask
| #define PWM_BRKCTL4_5_BRKAODD_Pos (18) |
PWM_T::BRKCTL4_5: BRKAODD Position
| #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) |
PWM_T::BRKCTL4_5: BRKP0EEN Mask
| #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL4_5: BRKP0EEN Position
| #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) |
PWM_T::BRKCTL4_5: BRKP0LEN Mask
| #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL4_5: BRKP0LEN Position
| #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) |
PWM_T::BRKCTL4_5: BRKP1EEN Mask
| #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL4_5: BRKP1EEN Position
| #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) |
PWM_T::BRKCTL4_5: BRKP1LEN Mask
| #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL4_5: BRKP1LEN Position
| #define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) |
PWM_T::BRKCTL4_5: SYSEBEN Mask
| #define PWM_BRKCTL4_5_SYSEBEN_Pos (7) |
PWM_T::BRKCTL4_5: SYSEBEN Position
| #define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) |
PWM_T::BRKCTL4_5: SYSLBEN Mask
| #define PWM_BRKCTL4_5_SYSLBEN_Pos (15) |
PWM_T::BRKCTL4_5: SYSLBEN Position
| #define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) |
PWM_T::CAPCTL: CAPEN0 Mask
| #define PWM_CAPCTL_CAPEN0_Pos (0) |
PWM_T::CAPCTL: CAPEN0 Position
| #define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) |
PWM_T::CAPCTL: CAPEN1 Mask
| #define PWM_CAPCTL_CAPEN1_Pos (1) |
PWM_T::CAPCTL: CAPEN1 Position
| #define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) |
PWM_T::CAPCTL: CAPEN2 Mask
| #define PWM_CAPCTL_CAPEN2_Pos (2) |
PWM_T::CAPCTL: CAPEN2 Position
| #define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) |
PWM_T::CAPCTL: CAPEN3 Mask
| #define PWM_CAPCTL_CAPEN3_Pos (3) |
PWM_T::CAPCTL: CAPEN3 Position
| #define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) |
PWM_T::CAPCTL: CAPEN4 Mask
| #define PWM_CAPCTL_CAPEN4_Pos (4) |
PWM_T::CAPCTL: CAPEN4 Position
| #define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) |
PWM_T::CAPCTL: CAPEN5 Mask
| #define PWM_CAPCTL_CAPEN5_Pos (5) |
PWM_T::CAPCTL: CAPEN5 Position
| #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) |
PWM_T::CAPCTL: CAPENn Mask
| #define PWM_CAPCTL_CAPENn_Pos (0) |
PWM_T::CAPCTL: CAPENn Position
| #define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) |
PWM_T::CAPCTL: CAPINV0 Mask
| #define PWM_CAPCTL_CAPINV0_Pos (8) |
PWM_T::CAPCTL: CAPINV0 Position
| #define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) |
PWM_T::CAPCTL: CAPINV1 Mask
| #define PWM_CAPCTL_CAPINV1_Pos (9) |
PWM_T::CAPCTL: CAPINV1 Position
| #define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) |
PWM_T::CAPCTL: CAPINV2 Mask
| #define PWM_CAPCTL_CAPINV2_Pos (10) |
PWM_T::CAPCTL: CAPINV2 Position
| #define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) |
PWM_T::CAPCTL: CAPINV3 Mask
| #define PWM_CAPCTL_CAPINV3_Pos (11) |
PWM_T::CAPCTL: CAPINV3 Position
| #define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) |
PWM_T::CAPCTL: CAPINV4 Mask
| #define PWM_CAPCTL_CAPINV4_Pos (12) |
PWM_T::CAPCTL: CAPINV4 Position
| #define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) |
PWM_T::CAPCTL: CAPINV5 Mask
| #define PWM_CAPCTL_CAPINV5_Pos (13) |
PWM_T::CAPCTL: CAPINV5 Position
| #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) |
PWM_T::CAPCTL: CAPINVn Mask
| #define PWM_CAPCTL_CAPINVn_Pos (8) |
PWM_T::CAPCTL: CAPINVn Position
| #define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) |
PWM_T::CAPCTL: FCRLDEN0 Mask
| #define PWM_CAPCTL_FCRLDEN0_Pos (24) |
PWM_T::CAPCTL: FCRLDEN0 Position
| #define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) |
PWM_T::CAPCTL: FCRLDEN1 Mask
| #define PWM_CAPCTL_FCRLDEN1_Pos (25) |
PWM_T::CAPCTL: FCRLDEN1 Position
| #define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) |
PWM_T::CAPCTL: FCRLDEN2 Mask
| #define PWM_CAPCTL_FCRLDEN2_Pos (26) |
PWM_T::CAPCTL: FCRLDEN2 Position
| #define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) |
PWM_T::CAPCTL: FCRLDEN3 Mask
| #define PWM_CAPCTL_FCRLDEN3_Pos (27) |
PWM_T::CAPCTL: FCRLDEN3 Position
| #define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) |
PWM_T::CAPCTL: FCRLDEN4 Mask
| #define PWM_CAPCTL_FCRLDEN4_Pos (28) |
PWM_T::CAPCTL: FCRLDEN4 Position
| #define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) |
PWM_T::CAPCTL: FCRLDEN5 Mask
| #define PWM_CAPCTL_FCRLDEN5_Pos (29) |
PWM_T::CAPCTL: FCRLDEN5 Position
| #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) |
PWM_T::CAPCTL: FCRLDENn Mask
| #define PWM_CAPCTL_FCRLDENn_Pos (24) |
PWM_T::CAPCTL: FCRLDENn Position
| #define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) |
PWM_T::CAPCTL: RCRLDEN0 Mask
| #define PWM_CAPCTL_RCRLDEN0_Pos (16) |
PWM_T::CAPCTL: RCRLDEN0 Position
| #define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) |
PWM_T::CAPCTL: RCRLDEN1 Mask
| #define PWM_CAPCTL_RCRLDEN1_Pos (17) |
PWM_T::CAPCTL: RCRLDEN1 Position
| #define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) |
PWM_T::CAPCTL: RCRLDEN2 Mask
| #define PWM_CAPCTL_RCRLDEN2_Pos (18) |
PWM_T::CAPCTL: RCRLDEN2 Position
| #define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) |
PWM_T::CAPCTL: RCRLDEN3 Mask
| #define PWM_CAPCTL_RCRLDEN3_Pos (19) |
PWM_T::CAPCTL: RCRLDEN3 Position
| #define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) |
PWM_T::CAPCTL: RCRLDEN4 Mask
| #define PWM_CAPCTL_RCRLDEN4_Pos (20) |
PWM_T::CAPCTL: RCRLDEN4 Position
| #define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) |
PWM_T::CAPCTL: RCRLDEN5 Mask
| #define PWM_CAPCTL_RCRLDEN5_Pos (21) |
PWM_T::CAPCTL: RCRLDEN5 Position
| #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) |
PWM_T::CAPCTL: RCRLDENn Mask
| #define PWM_CAPCTL_RCRLDENn_Pos (16) |
PWM_T::CAPCTL: RCRLDENn Position
| #define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) |
PWM_T::CAPIEN: CAPFIEN0 Mask
| #define PWM_CAPIEN_CAPFIEN0_Pos (8) |
PWM_T::CAPIEN: CAPFIEN0 Position
| #define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) |
PWM_T::CAPIEN: CAPFIEN1 Mask
| #define PWM_CAPIEN_CAPFIEN1_Pos (9) |
PWM_T::CAPIEN: CAPFIEN1 Position
| #define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) |
PWM_T::CAPIEN: CAPFIEN2 Mask
| #define PWM_CAPIEN_CAPFIEN2_Pos (10) |
PWM_T::CAPIEN: CAPFIEN2 Position
| #define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) |
PWM_T::CAPIEN: CAPFIEN3 Mask
| #define PWM_CAPIEN_CAPFIEN3_Pos (11) |
PWM_T::CAPIEN: CAPFIEN3 Position
| #define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) |
PWM_T::CAPIEN: CAPFIEN4 Mask
| #define PWM_CAPIEN_CAPFIEN4_Pos (12) |
PWM_T::CAPIEN: CAPFIEN4 Position
| #define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) |
PWM_T::CAPIEN: CAPFIEN5 Mask
| #define PWM_CAPIEN_CAPFIEN5_Pos (13) |
PWM_T::CAPIEN: CAPFIEN5 Position
| #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) |
PWM_T::CAPIEN: CAPFIENn Mask
| #define PWM_CAPIEN_CAPFIENn_Pos (8) |
PWM_T::CAPIEN: CAPFIENn Position
| #define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) |
PWM_T::CAPIEN: CAPRIEN0 Mask
| #define PWM_CAPIEN_CAPRIEN0_Pos (0) |
PWM_T::CAPIEN: CAPRIEN0 Position
| #define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) |
PWM_T::CAPIEN: CAPRIEN1 Mask
| #define PWM_CAPIEN_CAPRIEN1_Pos (1) |
PWM_T::CAPIEN: CAPRIEN1 Position
| #define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) |
PWM_T::CAPIEN: CAPRIEN2 Mask
| #define PWM_CAPIEN_CAPRIEN2_Pos (2) |
PWM_T::CAPIEN: CAPRIEN2 Position
| #define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) |
PWM_T::CAPIEN: CAPRIEN3 Mask
| #define PWM_CAPIEN_CAPRIEN3_Pos (3) |
PWM_T::CAPIEN: CAPRIEN3 Position
| #define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) |
PWM_T::CAPIEN: CAPRIEN4 Mask
| #define PWM_CAPIEN_CAPRIEN4_Pos (4) |
PWM_T::CAPIEN: CAPRIEN4 Position
| #define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) |
PWM_T::CAPIEN: CAPRIEN5 Mask
| #define PWM_CAPIEN_CAPRIEN5_Pos (5) |
PWM_T::CAPIEN: CAPRIEN5 Position
| #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) |
PWM_T::CAPIEN: CAPRIENn Mask
| #define PWM_CAPIEN_CAPRIENn_Pos (0) |
PWM_T::CAPIEN: CAPRIENn Position
| #define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) |
PWM_T::CAPIF: CFLIF0 Mask
| #define PWM_CAPIF_CFLIF0_Pos (8) |
PWM_T::CAPIF: CFLIF0 Position
| #define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) |
PWM_T::CAPIF: CFLIF1 Mask
| #define PWM_CAPIF_CFLIF1_Pos (9) |
PWM_T::CAPIF: CFLIF1 Position
| #define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) |
PWM_T::CAPIF: CFLIF2 Mask
| #define PWM_CAPIF_CFLIF2_Pos (10) |
PWM_T::CAPIF: CFLIF2 Position
| #define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) |
PWM_T::CAPIF: CFLIF3 Mask
| #define PWM_CAPIF_CFLIF3_Pos (11) |
PWM_T::CAPIF: CFLIF3 Position
| #define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) |
PWM_T::CAPIF: CFLIF4 Mask
| #define PWM_CAPIF_CFLIF4_Pos (12) |
PWM_T::CAPIF: CFLIF4 Position
| #define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) |
PWM_T::CAPIF: CFLIF5 Mask
| #define PWM_CAPIF_CFLIF5_Pos (13) |
PWM_T::CAPIF: CFLIF5 Position
| #define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) |
PWM_T::CAPIF: CFLIFn Mask
| #define PWM_CAPIF_CFLIFn_Pos (8) |
PWM_T::CAPIF: CFLIFn Position
| #define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) |
PWM_T::CAPIF: CRLIF0 Mask
| #define PWM_CAPIF_CRLIF0_Pos (0) |
PWM_T::CAPIF: CRLIF0 Position
| #define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) |
PWM_T::CAPIF: CRLIF1 Mask
| #define PWM_CAPIF_CRLIF1_Pos (1) |
PWM_T::CAPIF: CRLIF1 Position
| #define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) |
PWM_T::CAPIF: CRLIF2 Mask
| #define PWM_CAPIF_CRLIF2_Pos (2) |
PWM_T::CAPIF: CRLIF2 Position
| #define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) |
PWM_T::CAPIF: CRLIF3 Mask
| #define PWM_CAPIF_CRLIF3_Pos (3) |
PWM_T::CAPIF: CRLIF3 Position
| #define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) |
PWM_T::CAPIF: CRLIF4 Mask
| #define PWM_CAPIF_CRLIF4_Pos (4) |
PWM_T::CAPIF: CRLIF4 Position
| #define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) |
PWM_T::CAPIF: CRLIF5 Mask
| #define PWM_CAPIF_CRLIF5_Pos (5) |
PWM_T::CAPIF: CRLIF5 Position
| #define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) |
PWM_T::CAPIF: CRLIFn Mask
| #define PWM_CAPIF_CRLIFn_Pos (0) |
PWM_T::CAPIF: CRLIFn Position
| #define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) |
PWM_T::CAPINEN: CAPINEN0 Mask
| #define PWM_CAPINEN_CAPINEN0_Pos (0) |
PWM_T::CAPINEN: CAPINEN0 Position
| #define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) |
PWM_T::CAPINEN: CAPINEN1 Mask
| #define PWM_CAPINEN_CAPINEN1_Pos (1) |
PWM_T::CAPINEN: CAPINEN1 Position
| #define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) |
PWM_T::CAPINEN: CAPINEN2 Mask
| #define PWM_CAPINEN_CAPINEN2_Pos (2) |
PWM_T::CAPINEN: CAPINEN2 Position
| #define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) |
PWM_T::CAPINEN: CAPINEN3 Mask
| #define PWM_CAPINEN_CAPINEN3_Pos (3) |
PWM_T::CAPINEN: CAPINEN3 Position
| #define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) |
PWM_T::CAPINEN: CAPINEN4 Mask
| #define PWM_CAPINEN_CAPINEN4_Pos (4) |
PWM_T::CAPINEN: CAPINEN4 Position
| #define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) |
PWM_T::CAPINEN: CAPINEN5 Mask
| #define PWM_CAPINEN_CAPINEN5_Pos (5) |
PWM_T::CAPINEN: CAPINEN5 Position
| #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) |
PWM_T::CAPINEN: CAPINENn Mask
| #define PWM_CAPINEN_CAPINENn_Pos (0) |
PWM_T::CAPINEN: CAPINENn Position
| #define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) |
PWM_T::CAPSTS: CFLIFOV0 Mask
| #define PWM_CAPSTS_CFLIFOV0_Pos (8) |
PWM_T::CAPSTS: CFLIFOV0 Position
| #define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) |
PWM_T::CAPSTS: CFLIFOV1 Mask
| #define PWM_CAPSTS_CFLIFOV1_Pos (9) |
PWM_T::CAPSTS: CFLIFOV1 Position
| #define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) |
PWM_T::CAPSTS: CFLIFOV2 Mask
| #define PWM_CAPSTS_CFLIFOV2_Pos (10) |
PWM_T::CAPSTS: CFLIFOV2 Position
| #define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) |
PWM_T::CAPSTS: CFLIFOV3 Mask
| #define PWM_CAPSTS_CFLIFOV3_Pos (11) |
PWM_T::CAPSTS: CFLIFOV3 Position
| #define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) |
PWM_T::CAPSTS: CFLIFOV4 Mask
| #define PWM_CAPSTS_CFLIFOV4_Pos (12) |
PWM_T::CAPSTS: CFLIFOV4 Position
| #define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) |
PWM_T::CAPSTS: CFLIFOV5 Mask
| #define PWM_CAPSTS_CFLIFOV5_Pos (13) |
PWM_T::CAPSTS: CFLIFOV5 Position
| #define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) |
PWM_T::CAPSTS: CFLIFOVn Mask
| #define PWM_CAPSTS_CFLIFOVn_Pos (8) |
PWM_T::CAPSTS: CFLIFOVn Position
| #define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) |
PWM_T::CAPSTS: CRLIFOV0 Mask
| #define PWM_CAPSTS_CRLIFOV0_Pos (0) |
PWM_T::CAPSTS: CRLIFOV0 Position
| #define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) |
PWM_T::CAPSTS: CRLIFOV1 Mask
| #define PWM_CAPSTS_CRLIFOV1_Pos (1) |
PWM_T::CAPSTS: CRLIFOV1 Position
| #define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) |
PWM_T::CAPSTS: CRLIFOV2 Mask
| #define PWM_CAPSTS_CRLIFOV2_Pos (2) |
PWM_T::CAPSTS: CRLIFOV2 Position
| #define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) |
PWM_T::CAPSTS: CRLIFOV3 Mask
| #define PWM_CAPSTS_CRLIFOV3_Pos (3) |
PWM_T::CAPSTS: CRLIFOV3 Position
| #define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) |
PWM_T::CAPSTS: CRLIFOV4 Mask
| #define PWM_CAPSTS_CRLIFOV4_Pos (4) |
PWM_T::CAPSTS: CRLIFOV4 Position
| #define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) |
PWM_T::CAPSTS: CRLIFOV5 Mask
| #define PWM_CAPSTS_CRLIFOV5_Pos (5) |
PWM_T::CAPSTS: CRLIFOV5 Position
| #define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) |
PWM_T::CAPSTS: CRLIFOVn Mask
| #define PWM_CAPSTS_CRLIFOVn_Pos (0) |
PWM_T::CAPSTS: CRLIFOVn Position
| #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) |
PWM_T::CLKPSC0_1: CLKPSC Mask
| #define PWM_CLKPSC0_1_CLKPSC_Pos (0) |
PWM_T::CLKPSC0_1: CLKPSC Position
| #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) |
PWM_T::CLKPSC2_3: CLKPSC Mask
| #define PWM_CLKPSC2_3_CLKPSC_Pos (0) |
PWM_T::CLKPSC2_3: CLKPSC Position
| #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) |
PWM_T::CLKPSC4_5: CLKPSC Mask
| #define PWM_CLKPSC4_5_CLKPSC_Pos (0) |
PWM_T::CLKPSC4_5: CLKPSC Position
| #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) |
PWM_T::CLKSRC: ECLKSRC0 Mask
| #define PWM_CLKSRC_ECLKSRC0_Pos (0) |
PWM_T::CLKSRC: ECLKSRC0 Position
| #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) |
PWM_T::CLKSRC: ECLKSRC2 Mask
| #define PWM_CLKSRC_ECLKSRC2_Pos (8) |
PWM_T::CLKSRC: ECLKSRC2 Position
| #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) |
PWM_T::CLKSRC: ECLKSRC4 Mask
| #define PWM_CLKSRC_ECLKSRC4_Pos (16) |
PWM_T::CLKSRC: ECLKSRC4 Position
| #define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) |
PWM_T::CMPBUF: CMPBUF Mask
| #define PWM_CMPBUF_CMPBUF_Pos (0) |
PWM_T::CMPBUF: CMPBUF Position
| #define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) |
PWM_T::CMPDAT: CMP Mask
| #define PWM_CMPDAT_CMP_Pos (0) |
PWM_T::CMPDAT: CMP Position
| #define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) |
PWM_T::CNT: CNT Mask
| #define PWM_CNT_CNT_Pos (0) |
PWM_T::CNT: CNT Position
| #define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) |
PWM_T::CNT: DIRF Mask
| #define PWM_CNT_DIRF_Pos (16) |
PWM_T::CNT: DIRF Position
| #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) |
PWM_T::CNTCLR: CNTCLR0 Mask
| #define PWM_CNTCLR_CNTCLR0_Pos (0) |
PWM_T::CNTCLR: CNTCLR0 Position
| #define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) |
PWM_T::CNTCLR: CNTCLR1 Mask
| #define PWM_CNTCLR_CNTCLR1_Pos (1) |
PWM_T::CNTCLR: CNTCLR1 Position
| #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) |
PWM_T::CNTCLR: CNTCLR2 Mask
| #define PWM_CNTCLR_CNTCLR2_Pos (2) |
PWM_T::CNTCLR: CNTCLR2 Position
| #define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) |
PWM_T::CNTCLR: CNTCLR3 Mask
| #define PWM_CNTCLR_CNTCLR3_Pos (3) |
PWM_T::CNTCLR: CNTCLR3 Position
| #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) |
PWM_T::CNTCLR: CNTCLR4 Mask
| #define PWM_CNTCLR_CNTCLR4_Pos (4) |
PWM_T::CNTCLR: CNTCLR4 Position
| #define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) |
PWM_T::CNTCLR: CNTCLR5 Mask
| #define PWM_CNTCLR_CNTCLR5_Pos (5) |
PWM_T::CNTCLR: CNTCLR5 Position
| #define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) |
PWM_T::CNTCLR: CNTCLRn Mask
| #define PWM_CNTCLR_CNTCLRn_Pos (0) |
PWM_T::CNTCLR: CNTCLRn Position
| #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) |
PWM_T::CNTEN: CNTEN0 Mask
| #define PWM_CNTEN_CNTEN0_Pos (0) |
PWM_T::CNTEN: CNTEN0 Position
| #define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) |
PWM_T::CNTEN: CNTEN1 Mask
| #define PWM_CNTEN_CNTEN1_Pos (1) |
PWM_T::CNTEN: CNTEN1 Position
| #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) |
PWM_T::CNTEN: CNTEN2 Mask
| #define PWM_CNTEN_CNTEN2_Pos (2) |
PWM_T::CNTEN: CNTEN2 Position
| #define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) |
PWM_T::CNTEN: CNTEN3 Mask
| #define PWM_CNTEN_CNTEN3_Pos (3) |
PWM_T::CNTEN: CNTEN3 Position
| #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) |
PWM_T::CNTEN: CNTEN4 Mask
| #define PWM_CNTEN_CNTEN4_Pos (4) |
PWM_T::CNTEN: CNTEN4 Position
| #define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) |
PWM_T::CNTEN: CNTEN5 Mask
| #define PWM_CNTEN_CNTEN5_Pos (5) |
PWM_T::CNTEN: CNTEN5 Position
| #define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) |
PWM_T::CNTEN: CNTENn Mask
| #define PWM_CNTEN_CNTENn_Pos (0) |
PWM_T::CNTEN: CNTENn Position
| #define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) |
PWM_T::CTL0: CTRLD0 Mask
| #define PWM_CTL0_CTRLD0_Pos (0) |
PWM_T::CTL0: CTRLD0 Position
| #define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) |
PWM_T::CTL0: CTRLD1 Mask
| #define PWM_CTL0_CTRLD1_Pos (1) |
PWM_T::CTL0: CTRLD1 Position
| #define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) |
PWM_T::CTL0: CTRLD2 Mask
| #define PWM_CTL0_CTRLD2_Pos (2) |
PWM_T::CTL0: CTRLD2 Position
| #define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) |
PWM_T::CTL0: CTRLD3 Mask
| #define PWM_CTL0_CTRLD3_Pos (3) |
PWM_T::CTL0: CTRLD3 Position
| #define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) |
PWM_T::CTL0: CTRLD4 Mask
| #define PWM_CTL0_CTRLD4_Pos (4) |
PWM_T::CTL0: CTRLD4 Position
| #define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) |
PWM_T::CTL0: CTRLD5 Mask
| #define PWM_CTL0_CTRLD5_Pos (5) |
PWM_T::CTL0: CTRLD5 Position
| #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) |
PWM_T::CTL0: CTRLDn Mask
| #define PWM_CTL0_CTRLDn_Pos (0) |
@addtogroup PWM_CONST PWM Bit Field Definition Constant Definitions for PWM Controller
PWM_T::CTL0: CTRLDn Position
| #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) |
PWM_T::CTL0: DBGHALT Mask
| #define PWM_CTL0_DBGHALT_Pos (30) |
PWM_T::CTL0: DBGHALT Position
| #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) |
PWM_T::CTL0: DBGTRIOFF Mask
| #define PWM_CTL0_DBGTRIOFF_Pos (31) |
PWM_T::CTL0: DBGTRIOFF Position
| #define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) |
PWM_T::CTL0: GROUPEN Mask
| #define PWM_CTL0_GROUPEN_Pos (24) |
PWM_T::CTL0: GROUPEN Position
| #define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) |
PWM_T::CTL0: IMMLDEN0 Mask
| #define PWM_CTL0_IMMLDEN0_Pos (16) |
PWM_T::CTL0: IMMLDEN0 Position
| #define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) |
PWM_T::CTL0: IMMLDEN1 Mask
| #define PWM_CTL0_IMMLDEN1_Pos (17) |
PWM_T::CTL0: IMMLDEN1 Position
| #define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) |
PWM_T::CTL0: IMMLDEN2 Mask
| #define PWM_CTL0_IMMLDEN2_Pos (18) |
PWM_T::CTL0: IMMLDEN2 Position
| #define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) |
PWM_T::CTL0: IMMLDEN3 Mask
| #define PWM_CTL0_IMMLDEN3_Pos (19) |
PWM_T::CTL0: IMMLDEN3 Position
| #define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) |
PWM_T::CTL0: IMMLDEN4 Mask
| #define PWM_CTL0_IMMLDEN4_Pos (20) |
PWM_T::CTL0: IMMLDEN4 Position
| #define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) |
PWM_T::CTL0: IMMLDEN5 Mask
| #define PWM_CTL0_IMMLDEN5_Pos (21) |
PWM_T::CTL0: IMMLDEN5 Position
| #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) |
PWM_T::CTL0: IMMLDENn Mask
| #define PWM_CTL0_IMMLDENn_Pos (16) |
PWM_T::CTL0: IMMLDENn Position
| #define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) |
PWM_T::CTL0: WINLDEN0 Mask
| #define PWM_CTL0_WINLDEN0_Pos (8) |
PWM_T::CTL0: WINLDEN0 Position
| #define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) |
PWM_T::CTL0: WINLDEN1 Mask
| #define PWM_CTL0_WINLDEN1_Pos (9) |
PWM_T::CTL0: WINLDEN1 Position
| #define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) |
PWM_T::CTL0: WINLDEN2 Mask
| #define PWM_CTL0_WINLDEN2_Pos (10) |
PWM_T::CTL0: WINLDEN2 Position
| #define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) |
PWM_T::CTL0: WINLDEN3 Mask
| #define PWM_CTL0_WINLDEN3_Pos (11) |
PWM_T::CTL0: WINLDEN3 Position
| #define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) |
PWM_T::CTL0: WINLDEN4 Mask
| #define PWM_CTL0_WINLDEN4_Pos (12) |
PWM_T::CTL0: WINLDEN4 Position
| #define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) |
PWM_T::CTL0: WINLDEN5 Mask
| #define PWM_CTL0_WINLDEN5_Pos (13) |
PWM_T::CTL0: WINLDEN5 Position
| #define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) |
PWM_T::CTL0: WINLDENn Mask
| #define PWM_CTL0_WINLDENn_Pos (8) |
PWM_T::CTL0: WINLDENn Position
| #define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) |
PWM_T::CTL1: CNTMODE0 Mask
| #define PWM_CTL1_CNTMODE0_Pos (16) |
PWM_T::CTL1: CNTMODE0 Position
| #define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) |
PWM_T::CTL1: CNTMODE1 Mask
| #define PWM_CTL1_CNTMODE1_Pos (17) |
PWM_T::CTL1: CNTMODE1 Position
| #define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) |
PWM_T::CTL1: CNTMODE2 Mask
| #define PWM_CTL1_CNTMODE2_Pos (18) |
PWM_T::CTL1: CNTMODE2 Position
| #define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) |
PWM_T::CTL1: CNTMODE3 Mask
| #define PWM_CTL1_CNTMODE3_Pos (19) |
PWM_T::CTL1: CNTMODE3 Position
| #define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) |
PWM_T::CTL1: CNTMODE4 Mask
| #define PWM_CTL1_CNTMODE4_Pos (20) |
PWM_T::CTL1: CNTMODE4 Position
| #define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) |
PWM_T::CTL1: CNTMODE5 Mask
| #define PWM_CTL1_CNTMODE5_Pos (21) |
PWM_T::CTL1: CNTMODE5 Position
| #define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) |
PWM_T::CTL1: CNTMODEn Mask
| #define PWM_CTL1_CNTMODEn_Pos (16) |
PWM_T::CTL1: CNTMODEn Position
| #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) |
PWM_T::CTL1: CNTTYPE0 Mask
| #define PWM_CTL1_CNTTYPE0_Pos (0) |
PWM_T::CTL1: CNTTYPE0 Position
| #define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) |
PWM_T::CTL1: CNTTYPE1 Mask
| #define PWM_CTL1_CNTTYPE1_Pos (2) |
PWM_T::CTL1: CNTTYPE1 Position
| #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) |
PWM_T::CTL1: CNTTYPE2 Mask
| #define PWM_CTL1_CNTTYPE2_Pos (4) |
PWM_T::CTL1: CNTTYPE2 Position
| #define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) |
PWM_T::CTL1: CNTTYPE3 Mask
| #define PWM_CTL1_CNTTYPE3_Pos (6) |
PWM_T::CTL1: CNTTYPE3 Position
| #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) |
PWM_T::CTL1: CNTTYPE4 Mask
| #define PWM_CTL1_CNTTYPE4_Pos (8) |
PWM_T::CTL1: CNTTYPE4 Position
| #define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) |
PWM_T::CTL1: CNTTYPE5 Mask
| #define PWM_CTL1_CNTTYPE5_Pos (10) |
PWM_T::CTL1: CNTTYPE5 Position
| #define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) |
PWM_T::CTL1: CNTTYPEn Mask
| #define PWM_CTL1_CNTTYPEn_Pos (0) |
PWM_T::CTL1: CNTTYPEn Position
| #define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) |
PWM_T::CTL1: OUTMODE0 Mask
| #define PWM_CTL1_OUTMODE0_Pos (24) |
PWM_T::CTL1: OUTMODE0 Position
| #define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) |
PWM_T::CTL1: OUTMODE2 Mask
| #define PWM_CTL1_OUTMODE2_Pos (25) |
PWM_T::CTL1: OUTMODE2 Position
| #define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) |
PWM_T::CTL1: OUTMODE4 Mask
| #define PWM_CTL1_OUTMODE4_Pos (26) |
PWM_T::CTL1: OUTMODE4 Position
| #define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) |
PWM_T::CTL1: OUTMODEn Mask
| #define PWM_CTL1_OUTMODEn_Pos (24) |
PWM_T::CTL1: OUTMODEn Position
| #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) |
PWM_T::DTCTL0_1: DTCKSEL Mask
| #define PWM_DTCTL0_1_DTCKSEL_Pos (24) |
PWM_T::DTCTL0_1: DTCKSEL Position
| #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) |
PWM_T::DTCTL0_1: DTCNT Mask
| #define PWM_DTCTL0_1_DTCNT_Pos (0) |
PWM_T::DTCTL0_1: DTCNT Position
| #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) |
PWM_T::DTCTL0_1: DTEN Mask
| #define PWM_DTCTL0_1_DTEN_Pos (16) |
PWM_T::DTCTL0_1: DTEN Position
| #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) |
PWM_T::DTCTL2_3: DTCKSEL Mask
| #define PWM_DTCTL2_3_DTCKSEL_Pos (24) |
PWM_T::DTCTL2_3: DTCKSEL Position
| #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) |
PWM_T::DTCTL2_3: DTCNT Mask
| #define PWM_DTCTL2_3_DTCNT_Pos (0) |
PWM_T::DTCTL2_3: DTCNT Position
| #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) |
PWM_T::DTCTL2_3: DTEN Mask
| #define PWM_DTCTL2_3_DTEN_Pos (16) |
PWM_T::DTCTL2_3: DTEN Position
| #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) |
PWM_T::DTCTL4_5: DTCKSEL Mask
| #define PWM_DTCTL4_5_DTCKSEL_Pos (24) |
PWM_T::DTCTL4_5: DTCKSEL Position
| #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) |
PWM_T::DTCTL4_5: DTCNT Mask
| #define PWM_DTCTL4_5_DTCNT_Pos (0) |
PWM_T::DTCTL4_5: DTCNT Position
| #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) |
PWM_T::DTCTL4_5: DTEN Mask
| #define PWM_DTCTL4_5_DTEN_Pos (16) |
PWM_T::DTCTL4_5: DTEN Position
| #define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) |
PWM_T::EADCTS0: TRGEN0 Mask
| #define PWM_EADCTS0_TRGEN0_Pos (7) |
PWM_T::EADCTS0: TRGEN0 Position
| #define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) |
PWM_T::EADCTS0: TRGEN1 Mask
| #define PWM_EADCTS0_TRGEN1_Pos (15) |
PWM_T::EADCTS0: TRGEN1 Position
| #define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) |
PWM_T::EADCTS0: TRGEN2 Mask
| #define PWM_EADCTS0_TRGEN2_Pos (23) |
PWM_T::EADCTS0: TRGEN2 Position
| #define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) |
PWM_T::EADCTS0: TRGEN3 Mask
| #define PWM_EADCTS0_TRGEN3_Pos (31) |
PWM_T::EADCTS0: TRGEN3 Position
| #define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) |
PWM_T::EADCTS0: TRGSEL0 Mask
| #define PWM_EADCTS0_TRGSEL0_Pos (0) |
PWM_T::EADCTS0: TRGSEL0 Position
| #define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) |
PWM_T::EADCTS0: TRGSEL1 Mask
| #define PWM_EADCTS0_TRGSEL1_Pos (8) |
PWM_T::EADCTS0: TRGSEL1 Position
| #define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) |
PWM_T::EADCTS0: TRGSEL2 Mask
| #define PWM_EADCTS0_TRGSEL2_Pos (16) |
PWM_T::EADCTS0: TRGSEL2 Position
| #define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) |
PWM_T::EADCTS0: TRGSEL3 Mask
| #define PWM_EADCTS0_TRGSEL3_Pos (24) |
PWM_T::EADCTS0: TRGSEL3 Position
| #define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) |
PWM_T::EADCTS1: TRGEN4 Mask
| #define PWM_EADCTS1_TRGEN4_Pos (7) |
PWM_T::EADCTS1: TRGEN4 Position
| #define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) |
PWM_T::EADCTS1: TRGEN5 Mask
| #define PWM_EADCTS1_TRGEN5_Pos (15) |
PWM_T::EADCTS1: TRGEN5 Position
| #define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) |
PWM_T::EADCTS1: TRGSEL4 Mask
| #define PWM_EADCTS1_TRGSEL4_Pos (0) |
PWM_T::EADCTS1: TRGSEL4 Position
| #define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) |
PWM_T::EADCTS1: TRGSEL5 Mask
| #define PWM_EADCTS1_TRGSEL5_Pos (8) |
PWM_T::EADCTS1: TRGSEL5 Position
| #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) |
PWM_T::FAILBRK: BODBRKEN Mask
| #define PWM_FAILBRK_BODBRKEN_Pos (1) |
PWM_T::FAILBRK: BODBRKEN Position
| #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) |
PWM_T::FAILBRK: CORBRKEN Mask
| #define PWM_FAILBRK_CORBRKEN_Pos (3) |
PWM_T::FAILBRK: CORBRKEN Position
| #define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) |
PWM_T::FAILBRK: CSSBRKEN Mask
| #define PWM_FAILBRK_CSSBRKEN_Pos (0) |
PWM_T::FAILBRK: CSSBRKEN Position
| #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) |
PWM_T::FCAPDAT0: FCAPDAT Mask
| #define PWM_FCAPDAT0_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT0: FCAPDAT Position
| #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) |
PWM_T::FCAPDAT1: FCAPDAT Mask
| #define PWM_FCAPDAT1_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT1: FCAPDAT Position
| #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) |
PWM_T::FCAPDAT2: FCAPDAT Mask
| #define PWM_FCAPDAT2_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT2: FCAPDAT Position
| #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) |
PWM_T::FCAPDAT3: FCAPDAT Mask
| #define PWM_FCAPDAT3_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT3: FCAPDAT Position
| #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) |
PWM_T::FCAPDAT4: FCAPDAT Mask
| #define PWM_FCAPDAT4_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT4: FCAPDAT Position
| #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) |
PWM_T::FCAPDAT5: FCAPDAT Mask
| #define PWM_FCAPDAT5_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT5: FCAPDAT Position
| #define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) |
PWM_T::FTCBUF0_1: FTCMPBUF Mask
| #define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) |
PWM_T::FTCBUF0_1: FTCMPBUF Position
| #define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) |
PWM_T::FTCBUF2_3: FTCMPBUF Mask
| #define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) |
PWM_T::FTCBUF2_3: FTCMPBUF Position
| #define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) |
PWM_T::FTCBUF4_5: FTCMPBUF Mask
| #define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) |
PWM_T::FTCBUF4_5: FTCMPBUF Position
| #define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) |
PWM_T::FTCI: FTCMD0 Mask
| #define PWM_FTCI_FTCMD0_Pos (8) |
PWM_T::FTCI: FTCMD0 Position
| #define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) |
PWM_T::FTCI: FTCMD2 Mask
| #define PWM_FTCI_FTCMD2_Pos (9) |
PWM_T::FTCI: FTCMD2 Position
| #define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) |
PWM_T::FTCI: FTCMD4 Mask
| #define PWM_FTCI_FTCMD4_Pos (10) |
PWM_T::FTCI: FTCMD4 Position
| #define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) |
PWM_T::FTCI: FTCMDn Mask
| #define PWM_FTCI_FTCMDn_Pos (8) |
PWM_T::FTCI: FTCMDn Position
| #define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) |
PWM_T::FTCI: FTCMU0 Mask
| #define PWM_FTCI_FTCMU0_Pos (0) |
PWM_T::FTCI: FTCMU0 Position
| #define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) |
PWM_T::FTCI: FTCMU2 Mask
| #define PWM_FTCI_FTCMU2_Pos (1) |
PWM_T::FTCI: FTCMU2 Position
| #define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) |
PWM_T::FTCI: FTCMU4 Mask
| #define PWM_FTCI_FTCMU4_Pos (2) |
PWM_T::FTCI: FTCMU4 Position
| #define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) |
PWM_T::FTCI: FTCMUn Mask
| #define PWM_FTCI_FTCMUn_Pos (0) |
PWM_T::FTCI: FTCMUn Position
| #define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) |
PWM_T::FTCMPDAT0_1: FTCMP Mask
| #define PWM_FTCMPDAT0_1_FTCMP_Pos (0) |
PWM_T::FTCMPDAT0_1: FTCMP Position
| #define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) |
PWM_T::FTCMPDAT2_3: FTCMP Mask
| #define PWM_FTCMPDAT2_3_FTCMP_Pos (0) |
PWM_T::FTCMPDAT2_3: FTCMP Position
| #define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) |
PWM_T::FTCMPDAT4_5: FTCMP Mask
| #define PWM_FTCMPDAT4_5_FTCMP_Pos (0) |
PWM_T::FTCMPDAT4_5: FTCMP Position
| #define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) |
PWM_T::IFA: IFAEN0_1 Mask
| #define PWM_IFA_IFAEN0_1_Pos (7) |
PWM_T::IFA: IFAEN0_1 Position
| #define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) |
PWM_T::IFA: IFAEN2_3 Mask
| #define PWM_IFA_IFAEN2_3_Pos (15) |
PWM_T::IFA: IFAEN2_3 Position
| #define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) |
PWM_T::IFA: IFAEN4_5 Mask
| #define PWM_IFA_IFAEN4_5_Pos (23) |
PWM_T::IFA: IFAEN4_5 Position
| #define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) |
PWM_T::IFA: IFCNT0_1 Mask
| #define PWM_IFA_IFCNT0_1_Pos (0) |
PWM_T::IFA: IFCNT0_1 Position
| #define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) |
PWM_T::IFA: IFCNT2_3 Mask
| #define PWM_IFA_IFCNT2_3_Pos (8) |
PWM_T::IFA: IFCNT2_3 Position
| #define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) |
PWM_T::IFA: IFCNT4_5 Mask
| #define PWM_IFA_IFCNT4_5_Pos (16) |
PWM_T::IFA: IFCNT4_5 Position
| #define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) |
PWM_T::IFA: IFSEL0_1 Mask
| #define PWM_IFA_IFSEL0_1_Pos (4) |
PWM_T::IFA: IFSEL0_1 Position
| #define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) |
PWM_T::IFA: IFSEL2_3 Mask
| #define PWM_IFA_IFSEL2_3_Pos (12) |
PWM_T::IFA: IFSEL2_3 Position
| #define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) |
PWM_T::IFA: IFSEL4_5 Mask
| #define PWM_IFA_IFSEL4_5_Pos (20) |
PWM_T::IFA: IFSEL4_5 Position
| #define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) |
PWM_T::INTEN0: CMPDIEN0 Mask
| #define PWM_INTEN0_CMPDIEN0_Pos (24) |
PWM_T::INTEN0: CMPDIEN0 Position
| #define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) |
PWM_T::INTEN0: CMPDIEN1 Mask
| #define PWM_INTEN0_CMPDIEN1_Pos (25) |
PWM_T::INTEN0: CMPDIEN1 Position
| #define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) |
PWM_T::INTEN0: CMPDIEN2 Mask
| #define PWM_INTEN0_CMPDIEN2_Pos (26) |
PWM_T::INTEN0: CMPDIEN2 Position
| #define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) |
PWM_T::INTEN0: CMPDIEN3 Mask
| #define PWM_INTEN0_CMPDIEN3_Pos (27) |
PWM_T::INTEN0: CMPDIEN3 Position
| #define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) |
PWM_T::INTEN0: CMPDIEN4 Mask
| #define PWM_INTEN0_CMPDIEN4_Pos (28) |
PWM_T::INTEN0: CMPDIEN4 Position
| #define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) |
PWM_T::INTEN0: CMPDIEN5 Mask
| #define PWM_INTEN0_CMPDIEN5_Pos (29) |
PWM_T::INTEN0: CMPDIEN5 Position
| #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) |
PWM_T::INTEN0: CMPDIENn Mask
| #define PWM_INTEN0_CMPDIENn_Pos (24) |
PWM_T::INTEN0: CMPDIENn Position
| #define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) |
PWM_T::INTEN0: CMPUIEN0 Mask
| #define PWM_INTEN0_CMPUIEN0_Pos (16) |
PWM_T::INTEN0: CMPUIEN0 Position
| #define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) |
PWM_T::INTEN0: CMPUIEN1 Mask
| #define PWM_INTEN0_CMPUIEN1_Pos (17) |
PWM_T::INTEN0: CMPUIEN1 Position
| #define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) |
PWM_T::INTEN0: CMPUIEN2 Mask
| #define PWM_INTEN0_CMPUIEN2_Pos (18) |
PWM_T::INTEN0: CMPUIEN2 Position
| #define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) |
PWM_T::INTEN0: CMPUIEN3 Mask
| #define PWM_INTEN0_CMPUIEN3_Pos (19) |
PWM_T::INTEN0: CMPUIEN3 Position
| #define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) |
PWM_T::INTEN0: CMPUIEN4 Mask
| #define PWM_INTEN0_CMPUIEN4_Pos (20) |
PWM_T::INTEN0: CMPUIEN4 Position
| #define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) |
PWM_T::INTEN0: CMPUIEN5 Mask
| #define PWM_INTEN0_CMPUIEN5_Pos (21) |
PWM_T::INTEN0: CMPUIEN5 Position
| #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) |
PWM_T::INTEN0: CMPUIENn Mask
| #define PWM_INTEN0_CMPUIENn_Pos (16) |
PWM_T::INTEN0: CMPUIENn Position
| #define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) |
PWM_T::INTEN0: IFAIEN0_1 Mask
| #define PWM_INTEN0_IFAIEN0_1_Pos (7) |
PWM_T::INTEN0: IFAIEN0_1 Position
| #define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) |
PWM_T::INTEN0: IFAIEN2_3 Mask
| #define PWM_INTEN0_IFAIEN2_3_Pos (15) |
PWM_T::INTEN0: IFAIEN2_3 Position
| #define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) |
PWM_T::INTEN0: IFAIEN4_5 Mask
| #define PWM_INTEN0_IFAIEN4_5_Pos (23) |
PWM_T::INTEN0: IFAIEN4_5 Position
| #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) |
PWM_T::INTEN0: PIEN0 Mask
| #define PWM_INTEN0_PIEN0_Pos (8) |
PWM_T::INTEN0: PIEN0 Position
| #define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) |
PWM_T::INTEN0: PIEN1 Mask
| #define PWM_INTEN0_PIEN1_Pos (9) |
PWM_T::INTEN0: PIEN1 Position
| #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) |
PWM_T::INTEN0: PIEN2 Mask
| #define PWM_INTEN0_PIEN2_Pos (10) |
PWM_T::INTEN0: PIEN2 Position
| #define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) |
PWM_T::INTEN0: PIEN3 Mask
| #define PWM_INTEN0_PIEN3_Pos (11) |
PWM_T::INTEN0: PIEN3 Position
| #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) |
PWM_T::INTEN0: PIEN4 Mask
| #define PWM_INTEN0_PIEN4_Pos (12) |
PWM_T::INTEN0: PIEN4 Position
| #define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) |
PWM_T::INTEN0: PIEN5 Mask
| #define PWM_INTEN0_PIEN5_Pos (13) |
PWM_T::INTEN0: PIEN5 Position
| #define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) |
PWM_T::INTEN0: PIENn Mask
| #define PWM_INTEN0_PIENn_Pos (8) |
PWM_T::INTEN0: PIENn Position
| #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) |
PWM_T::INTEN0: ZIEN0 Mask
| #define PWM_INTEN0_ZIEN0_Pos (0) |
PWM_T::INTEN0: ZIEN0 Position
| #define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) |
PWM_T::INTEN0: ZIEN1 Mask
| #define PWM_INTEN0_ZIEN1_Pos (1) |
PWM_T::INTEN0: ZIEN1 Position
| #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) |
PWM_T::INTEN0: ZIEN2 Mask
| #define PWM_INTEN0_ZIEN2_Pos (2) |
PWM_T::INTEN0: ZIEN2 Position
| #define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) |
PWM_T::INTEN0: ZIEN3 Mask
| #define PWM_INTEN0_ZIEN3_Pos (3) |
PWM_T::INTEN0: ZIEN3 Position
| #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) |
PWM_T::INTEN0: ZIEN4 Mask
| #define PWM_INTEN0_ZIEN4_Pos (4) |
PWM_T::INTEN0: ZIEN4 Position
| #define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) |
PWM_T::INTEN0: ZIEN5 Mask
| #define PWM_INTEN0_ZIEN5_Pos (5) |
PWM_T::INTEN0: ZIEN5 Position
| #define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) |
PWM_T::INTEN0: ZIENn Mask
| #define PWM_INTEN0_ZIENn_Pos (0) |
PWM_T::INTEN0: ZIENn Position
| #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) |
PWM_T::INTEN1: BRKEIEN0_1 Mask
| #define PWM_INTEN1_BRKEIEN0_1_Pos (0) |
PWM_T::INTEN1: BRKEIEN0_1 Position
| #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) |
PWM_T::INTEN1: BRKEIEN2_3 Mask
| #define PWM_INTEN1_BRKEIEN2_3_Pos (1) |
PWM_T::INTEN1: BRKEIEN2_3 Position
| #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) |
PWM_T::INTEN1: BRKEIEN4_5 Mask
| #define PWM_INTEN1_BRKEIEN4_5_Pos (2) |
PWM_T::INTEN1: BRKEIEN4_5 Position
| #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) |
PWM_T::INTEN1: BRKLIEN0_1 Mask
| #define PWM_INTEN1_BRKLIEN0_1_Pos (8) |
PWM_T::INTEN1: BRKLIEN0_1 Position
| #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) |
PWM_T::INTEN1: BRKLIEN2_3 Mask
| #define PWM_INTEN1_BRKLIEN2_3_Pos (9) |
PWM_T::INTEN1: BRKLIEN2_3 Position
| #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) |
PWM_T::INTEN1: BRKLIEN4_5 Mask
| #define PWM_INTEN1_BRKLIEN4_5_Pos (10) |
PWM_T::INTEN1: BRKLIEN4_5 Position
| #define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) |
PWM_T::INTSTS0: CMPDIF0 Mask
| #define PWM_INTSTS0_CMPDIF0_Pos (24) |
PWM_T::INTSTS0: CMPDIF0 Position
| #define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) |
PWM_T::INTSTS0: CMPDIF1 Mask
| #define PWM_INTSTS0_CMPDIF1_Pos (25) |
PWM_T::INTSTS0: CMPDIF1 Position
| #define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) |
PWM_T::INTSTS0: CMPDIF2 Mask
| #define PWM_INTSTS0_CMPDIF2_Pos (26) |
PWM_T::INTSTS0: CMPDIF2 Position
| #define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) |
PWM_T::INTSTS0: CMPDIF3 Mask
| #define PWM_INTSTS0_CMPDIF3_Pos (27) |
PWM_T::INTSTS0: CMPDIF3 Position
| #define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) |
PWM_T::INTSTS0: CMPDIF4 Mask
| #define PWM_INTSTS0_CMPDIF4_Pos (28) |
PWM_T::INTSTS0: CMPDIF4 Position
| #define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) |
PWM_T::INTSTS0: CMPDIF5 Mask
| #define PWM_INTSTS0_CMPDIF5_Pos (29) |
PWM_T::INTSTS0: CMPDIF5 Position
| #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) |
PWM_T::INTSTS0: CMPDIFn Mask
| #define PWM_INTSTS0_CMPDIFn_Pos (24) |
PWM_T::INTSTS0: CMPDIFn Position
| #define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) |
PWM_T::INTSTS0: CMPUIF0 Mask
| #define PWM_INTSTS0_CMPUIF0_Pos (16) |
PWM_T::INTSTS0: CMPUIF0 Position
| #define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) |
PWM_T::INTSTS0: CMPUIF1 Mask
| #define PWM_INTSTS0_CMPUIF1_Pos (17) |
PWM_T::INTSTS0: CMPUIF1 Position
| #define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) |
PWM_T::INTSTS0: CMPUIF2 Mask
| #define PWM_INTSTS0_CMPUIF2_Pos (18) |
PWM_T::INTSTS0: CMPUIF2 Position
| #define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) |
PWM_T::INTSTS0: CMPUIF3 Mask
| #define PWM_INTSTS0_CMPUIF3_Pos (19) |
PWM_T::INTSTS0: CMPUIF3 Position
| #define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) |
PWM_T::INTSTS0: CMPUIF4 Mask
| #define PWM_INTSTS0_CMPUIF4_Pos (20) |
PWM_T::INTSTS0: CMPUIF4 Position
| #define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) |
PWM_T::INTSTS0: CMPUIF5 Mask
| #define PWM_INTSTS0_CMPUIF5_Pos (21) |
PWM_T::INTSTS0: CMPUIF5 Position
| #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) |
PWM_T::INTSTS0: CMPUIFn Mask
| #define PWM_INTSTS0_CMPUIFn_Pos (16) |
PWM_T::INTSTS0: CMPUIFn Position
| #define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) |
PWM_T::INTSTS0: IFAIF0_1 Mask
| #define PWM_INTSTS0_IFAIF0_1_Pos (7) |
PWM_T::INTSTS0: IFAIF0_1 Position
| #define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) |
PWM_T::INTSTS0: IFAIF2_3 Mask
| #define PWM_INTSTS0_IFAIF2_3_Pos (15) |
PWM_T::INTSTS0: IFAIF2_3 Position
| #define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) |
PWM_T::INTSTS0: IFAIF4_5 Mask
| #define PWM_INTSTS0_IFAIF4_5_Pos (23) |
PWM_T::INTSTS0: IFAIF4_5 Position
| #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) |
PWM_T::INTSTS0: PIF0 Mask
| #define PWM_INTSTS0_PIF0_Pos (8) |
PWM_T::INTSTS0: PIF0 Position
| #define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) |
PWM_T::INTSTS0: PIF1 Mask
| #define PWM_INTSTS0_PIF1_Pos (9) |
PWM_T::INTSTS0: PIF1 Position
| #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) |
PWM_T::INTSTS0: PIF2 Mask
| #define PWM_INTSTS0_PIF2_Pos (10) |
PWM_T::INTSTS0: PIF2 Position
| #define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) |
PWM_T::INTSTS0: PIF3 Mask
| #define PWM_INTSTS0_PIF3_Pos (11) |
PWM_T::INTSTS0: PIF3 Position
| #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) |
PWM_T::INTSTS0: PIF4 Mask
| #define PWM_INTSTS0_PIF4_Pos (12) |
PWM_T::INTSTS0: PIF4 Position
| #define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) |
PWM_T::INTSTS0: PIF5 Mask
| #define PWM_INTSTS0_PIF5_Pos (13) |
PWM_T::INTSTS0: PIF5 Position
| #define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) |
PWM_T::INTSTS0: PIFn Mask
| #define PWM_INTSTS0_PIFn_Pos (8) |
PWM_T::INTSTS0: PIFn Position
| #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) |
PWM_T::INTSTS0: ZIF0 Mask
| #define PWM_INTSTS0_ZIF0_Pos (0) |
PWM_T::INTSTS0: ZIF0 Position
| #define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) |
PWM_T::INTSTS0: ZIF1 Mask
| #define PWM_INTSTS0_ZIF1_Pos (1) |
PWM_T::INTSTS0: ZIF1 Position
| #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) |
PWM_T::INTSTS0: ZIF2 Mask
| #define PWM_INTSTS0_ZIF2_Pos (2) |
PWM_T::INTSTS0: ZIF2 Position
| #define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) |
PWM_T::INTSTS0: ZIF3 Mask
| #define PWM_INTSTS0_ZIF3_Pos (3) |
PWM_T::INTSTS0: ZIF3 Position
| #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) |
PWM_T::INTSTS0: ZIF4 Mask
| #define PWM_INTSTS0_ZIF4_Pos (4) |
PWM_T::INTSTS0: ZIF4 Position
| #define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) |
PWM_T::INTSTS0: ZIF5 Mask
| #define PWM_INTSTS0_ZIF5_Pos (5) |
PWM_T::INTSTS0: ZIF5 Position
| #define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) |
PWM_T::INTSTS0: ZIFn Mask
| #define PWM_INTSTS0_ZIFn_Pos (0) |
PWM_T::INTSTS0: ZIFn Position
| #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) |
PWM_T::INTSTS1: BRKEIF0 Mask
| #define PWM_INTSTS1_BRKEIF0_Pos (0) |
PWM_T::INTSTS1: BRKEIF0 Position
| #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) |
PWM_T::INTSTS1: BRKEIF1 Mask
| #define PWM_INTSTS1_BRKEIF1_Pos (1) |
PWM_T::INTSTS1: BRKEIF1 Position
| #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) |
PWM_T::INTSTS1: BRKEIF2 Mask
| #define PWM_INTSTS1_BRKEIF2_Pos (2) |
PWM_T::INTSTS1: BRKEIF2 Position
| #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) |
PWM_T::INTSTS1: BRKEIF3 Mask
| #define PWM_INTSTS1_BRKEIF3_Pos (3) |
PWM_T::INTSTS1: BRKEIF3 Position
| #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) |
PWM_T::INTSTS1: BRKEIF4 Mask
| #define PWM_INTSTS1_BRKEIF4_Pos (4) |
PWM_T::INTSTS1: BRKEIF4 Position
| #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) |
PWM_T::INTSTS1: BRKEIF5 Mask
| #define PWM_INTSTS1_BRKEIF5_Pos (5) |
PWM_T::INTSTS1: BRKEIF5 Position
| #define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) |
PWM_T::INTSTS1: BRKEIFn Mask
| #define PWM_INTSTS1_BRKEIFn_Pos (0) |
PWM_T::INTSTS1: BRKEIFn Position
| #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) |
PWM_T::INTSTS1: BRKESTS0 Mask
| #define PWM_INTSTS1_BRKESTS0_Pos (16) |
PWM_T::INTSTS1: BRKESTS0 Position
| #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) |
PWM_T::INTSTS1: BRKESTS1 Mask
| #define PWM_INTSTS1_BRKESTS1_Pos (17) |
PWM_T::INTSTS1: BRKESTS1 Position
| #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) |
PWM_T::INTSTS1: BRKESTS2 Mask
| #define PWM_INTSTS1_BRKESTS2_Pos (18) |
PWM_T::INTSTS1: BRKESTS2 Position
| #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) |
PWM_T::INTSTS1: BRKESTS3 Mask
| #define PWM_INTSTS1_BRKESTS3_Pos (19) |
PWM_T::INTSTS1: BRKESTS3 Position
| #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) |
PWM_T::INTSTS1: BRKESTS4 Mask
| #define PWM_INTSTS1_BRKESTS4_Pos (20) |
PWM_T::INTSTS1: BRKESTS4 Position
| #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) |
PWM_T::INTSTS1: BRKESTS5 Mask
| #define PWM_INTSTS1_BRKESTS5_Pos (21) |
PWM_T::INTSTS1: BRKESTS5 Position
| #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) |
PWM_T::INTSTS1: BRKLIF0 Mask
| #define PWM_INTSTS1_BRKLIF0_Pos (8) |
PWM_T::INTSTS1: BRKLIF0 Position
| #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) |
PWM_T::INTSTS1: BRKLIF1 Mask
| #define PWM_INTSTS1_BRKLIF1_Pos (9) |
PWM_T::INTSTS1: BRKLIF1 Position
| #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) |
PWM_T::INTSTS1: BRKLIF2 Mask
| #define PWM_INTSTS1_BRKLIF2_Pos (10) |
PWM_T::INTSTS1: BRKLIF2 Position
| #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) |
PWM_T::INTSTS1: BRKLIF3 Mask
| #define PWM_INTSTS1_BRKLIF3_Pos (11) |
PWM_T::INTSTS1: BRKLIF3 Position
| #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) |
PWM_T::INTSTS1: BRKLIF4 Mask
| #define PWM_INTSTS1_BRKLIF4_Pos (12) |
PWM_T::INTSTS1: BRKLIF4 Position
| #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) |
PWM_T::INTSTS1: BRKLIF5 Mask
| #define PWM_INTSTS1_BRKLIF5_Pos (13) |
PWM_T::INTSTS1: BRKLIF5 Position
| #define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) |
PWM_T::INTSTS1: BRKLIFn Mask
| #define PWM_INTSTS1_BRKLIFn_Pos (8) |
PWM_T::INTSTS1: BRKLIFn Position
| #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) |
PWM_T::INTSTS1: BRKLSTS0 Mask
| #define PWM_INTSTS1_BRKLSTS0_Pos (24) |
PWM_T::INTSTS1: BRKLSTS0 Position
| #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) |
PWM_T::INTSTS1: BRKLSTS1 Mask
| #define PWM_INTSTS1_BRKLSTS1_Pos (25) |
PWM_T::INTSTS1: BRKLSTS1 Position
| #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) |
PWM_T::INTSTS1: BRKLSTS2 Mask
| #define PWM_INTSTS1_BRKLSTS2_Pos (26) |
PWM_T::INTSTS1: BRKLSTS2 Position
| #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) |
PWM_T::INTSTS1: BRKLSTS3 Mask
| #define PWM_INTSTS1_BRKLSTS3_Pos (27) |
PWM_T::INTSTS1: BRKLSTS3 Position
| #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) |
PWM_T::INTSTS1: BRKLSTS4 Mask
| #define PWM_INTSTS1_BRKLSTS4_Pos (28) |
PWM_T::INTSTS1: BRKLSTS4 Position
| #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) |
PWM_T::INTSTS1: BRKLSTS5 Mask
| #define PWM_INTSTS1_BRKLSTS5_Pos (29) |
PWM_T::INTSTS1: BRKLSTS5 Position
| #define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) |
PWM_T::LOAD: LOAD0 Mask
| #define PWM_LOAD_LOAD0_Pos (0) |
PWM_T::LOAD: LOAD0 Position
| #define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) |
PWM_T::LOAD: LOAD1 Mask
| #define PWM_LOAD_LOAD1_Pos (1) |
PWM_T::LOAD: LOAD1 Position
| #define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) |
PWM_T::LOAD: LOAD2 Mask
| #define PWM_LOAD_LOAD2_Pos (2) |
PWM_T::LOAD: LOAD2 Position
| #define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) |
PWM_T::LOAD: LOAD3 Mask
| #define PWM_LOAD_LOAD3_Pos (3) |
PWM_T::LOAD: LOAD3 Position
| #define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) |
PWM_T::LOAD: LOAD4 Mask
| #define PWM_LOAD_LOAD4_Pos (4) |
PWM_T::LOAD: LOAD4 Position
| #define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) |
PWM_T::LOAD: LOAD5 Mask
| #define PWM_LOAD_LOAD5_Pos (5) |
PWM_T::LOAD: LOAD5 Position
| #define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) |
PWM_T::LOAD: LOADn Mask
| #define PWM_LOAD_LOADn_Pos (0) |
PWM_T::LOAD: LOADn Position
| #define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) |
PWM_T::MSK: MSKDAT0 Mask
| #define PWM_MSK_MSKDAT0_Pos (0) |
PWM_T::MSK: MSKDAT0 Position
| #define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) |
PWM_T::MSK: MSKDAT1 Mask
| #define PWM_MSK_MSKDAT1_Pos (1) |
PWM_T::MSK: MSKDAT1 Position
| #define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) |
PWM_T::MSK: MSKDAT2 Mask
| #define PWM_MSK_MSKDAT2_Pos (2) |
PWM_T::MSK: MSKDAT2 Position
| #define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) |
PWM_T::MSK: MSKDAT3 Mask
| #define PWM_MSK_MSKDAT3_Pos (3) |
PWM_T::MSK: MSKDAT3 Position
| #define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) |
PWM_T::MSK: MSKDAT4 Mask
| #define PWM_MSK_MSKDAT4_Pos (4) |
PWM_T::MSK: MSKDAT4 Position
| #define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) |
PWM_T::MSK: MSKDAT5 Mask
| #define PWM_MSK_MSKDAT5_Pos (5) |
PWM_T::MSK: MSKDAT5 Position
| #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) |
PWM_T::MSK: MSKDATn Mask
| #define PWM_MSK_MSKDATn_Pos (0) |
PWM_T::MSK: MSKDATn Position
| #define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) |
PWM_T::MSKEN: MSKEN0 Mask
| #define PWM_MSKEN_MSKEN0_Pos (0) |
PWM_T::MSKEN: MSKEN0 Position
| #define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) |
PWM_T::MSKEN: MSKEN1 Mask
| #define PWM_MSKEN_MSKEN1_Pos (1) |
PWM_T::MSKEN: MSKEN1 Position
| #define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) |
PWM_T::MSKEN: MSKEN2 Mask
| #define PWM_MSKEN_MSKEN2_Pos (2) |
PWM_T::MSKEN: MSKEN2 Position
| #define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) |
PWM_T::MSKEN: MSKEN3 Mask
| #define PWM_MSKEN_MSKEN3_Pos (3) |
PWM_T::MSKEN: MSKEN3 Position
| #define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) |
PWM_T::MSKEN: MSKEN4 Mask
| #define PWM_MSKEN_MSKEN4_Pos (4) |
PWM_T::MSKEN: MSKEN4 Position
| #define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) |
PWM_T::MSKEN: MSKEN5 Mask
| #define PWM_MSKEN_MSKEN5_Pos (5) |
PWM_T::MSKEN: MSKEN5 Position
| #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) |
PWM_T::MSKEN: MSKENn Mask
| #define PWM_MSKEN_MSKENn_Pos (0) |
PWM_T::MSKEN: MSKENn Position
| #define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) |
PWM_T::PBUF: PBUF Mask
| #define PWM_PBUF_PBUF_Pos (0) |
PWM_T::PBUF: PBUF Position
| #define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) |
PWM_T::PDMACAP0_1: CAPBUF Mask
| #define PWM_PDMACAP0_1_CAPBUF_Pos (0) |
PWM_T::PDMACAP0_1: CAPBUF Position
| #define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) |
PWM_T::PDMACAP2_3: CAPBUF Mask
| #define PWM_PDMACAP2_3_CAPBUF_Pos (0) |
PWM_T::PDMACAP2_3: CAPBUF Position
| #define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) |
PWM_T::PDMACAP4_5: CAPBUF Mask
| #define PWM_PDMACAP4_5_CAPBUF_Pos (0) |
PWM_T::PDMACAP4_5: CAPBUF Position
| #define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) |
PWM_T::PDMACTL: CAPMOD0_1 Mask
| #define PWM_PDMACTL_CAPMOD0_1_Pos (1) |
PWM_T::PDMACTL: CAPMOD0_1 Position
| #define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) |
PWM_T::PDMACTL: CAPMOD2_3 Mask
| #define PWM_PDMACTL_CAPMOD2_3_Pos (9) |
PWM_T::PDMACTL: CAPMOD2_3 Position
| #define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) |
PWM_T::PDMACTL: CAPMOD4_5 Mask
| #define PWM_PDMACTL_CAPMOD4_5_Pos (17) |
PWM_T::PDMACTL: CAPMOD4_5 Position
| #define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) |
PWM_T::PDMACTL: CAPORD0_1 Mask
| #define PWM_PDMACTL_CAPORD0_1_Pos (3) |
PWM_T::PDMACTL: CAPORD0_1 Position
| #define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) |
PWM_T::PDMACTL: CAPORD2_3 Mask
| #define PWM_PDMACTL_CAPORD2_3_Pos (11) |
PWM_T::PDMACTL: CAPORD2_3 Position
| #define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) |
PWM_T::PDMACTL: CAPORD4_5 Mask
| #define PWM_PDMACTL_CAPORD4_5_Pos (19) |
PWM_T::PDMACTL: CAPORD4_5 Position
| #define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) |
PWM_T::PDMACTL: CHEN0_1 Mask
| #define PWM_PDMACTL_CHEN0_1_Pos (0) |
PWM_T::PDMACTL: CHEN0_1 Position
| #define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) |
PWM_T::PDMACTL: CHEN2_3 Mask
| #define PWM_PDMACTL_CHEN2_3_Pos (8) |
PWM_T::PDMACTL: CHEN2_3 Position
| #define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) |
PWM_T::PDMACTL: CHEN4_5 Mask
| #define PWM_PDMACTL_CHEN4_5_Pos (16) |
PWM_T::PDMACTL: CHEN4_5 Position
| #define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) |
PWM_T::PDMACTL: CHSEL0_1 Mask
| #define PWM_PDMACTL_CHSEL0_1_Pos (4) |
PWM_T::PDMACTL: CHSEL0_1 Position
| #define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) |
PWM_T::PDMACTL: CHSEL2_3 Mask
| #define PWM_PDMACTL_CHSEL2_3_Pos (12) |
PWM_T::PDMACTL: CHSEL2_3 Position
| #define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) |
PWM_T::PDMACTL: CHSEL4_5 Mask
| #define PWM_PDMACTL_CHSEL4_5_Pos (20) |
PWM_T::PDMACTL: CHSEL4_5 Position
| #define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
| #define PWM_PERIOD_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
| #define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) |
PWM_T::PHS0_1: PHS Mask
| #define PWM_PHS0_1_PHS_Pos (0) |
PWM_T::PHS0_1: PHS Position
| #define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) |
PWM_T::PHS2_3: PHS Mask
| #define PWM_PHS2_3_PHS_Pos (0) |
PWM_T::PHS2_3: PHS Position
| #define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) |
PWM_T::PHS4_5: PHS Mask
| #define PWM_PHS4_5_PHS_Pos (0) |
PWM_T::PHS4_5: PHS Position
| #define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) |
PWM_T::POEN: POEN0 Mask
| #define PWM_POEN_POEN0_Pos (0) |
PWM_T::POEN: POEN0 Position
| #define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) |
PWM_T::POEN: POEN1 Mask
| #define PWM_POEN_POEN1_Pos (1) |
PWM_T::POEN: POEN1 Position
| #define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) |
PWM_T::POEN: POEN2 Mask
| #define PWM_POEN_POEN2_Pos (2) |
PWM_T::POEN: POEN2 Position
| #define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) |
PWM_T::POEN: POEN3 Mask
| #define PWM_POEN_POEN3_Pos (3) |
PWM_T::POEN: POEN3 Position
| #define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) |
PWM_T::POEN: POEN4 Mask
| #define PWM_POEN_POEN4_Pos (4) |
PWM_T::POEN: POEN4 Position
| #define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) |
PWM_T::POEN: POEN5 Mask
| #define PWM_POEN_POEN5_Pos (5) |
PWM_T::POEN: POEN5 Position
| #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) |
PWM_T::POEN: POENn Mask
| #define PWM_POEN_POENn_Pos (0) |
PWM_T::POEN: POENn Position
| #define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) |
PWM_T::POLCTL: PINV0 Mask
| #define PWM_POLCTL_PINV0_Pos (0) |
PWM_T::POLCTL: PINV0 Position
| #define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) |
PWM_T::POLCTL: PINV1 Mask
| #define PWM_POLCTL_PINV1_Pos (1) |
PWM_T::POLCTL: PINV1 Position
| #define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) |
PWM_T::POLCTL: PINV2 Mask
| #define PWM_POLCTL_PINV2_Pos (2) |
PWM_T::POLCTL: PINV2 Position
| #define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) |
PWM_T::POLCTL: PINV3 Mask
| #define PWM_POLCTL_PINV3_Pos (3) |
PWM_T::POLCTL: PINV3 Position
| #define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) |
PWM_T::POLCTL: PINV4 Mask
| #define PWM_POLCTL_PINV4_Pos (4) |
PWM_T::POLCTL: PINV4 Position
| #define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) |
PWM_T::POLCTL: PINV5 Mask
| #define PWM_POLCTL_PINV5_Pos (5) |
PWM_T::POLCTL: PINV5 Position
| #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) |
PWM_T::POLCTL: PINVn Mask
| #define PWM_POLCTL_PINVn_Pos (0) |
PWM_T::POLCTL: PINVn Position
| #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) |
PWM_T::RCAPDAT0: RCAPDAT Mask
| #define PWM_RCAPDAT0_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT0: RCAPDAT Position
| #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) |
PWM_T::RCAPDAT1: RCAPDAT Mask
| #define PWM_RCAPDAT1_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT1: RCAPDAT Position
| #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) |
PWM_T::RCAPDAT2: RCAPDAT Mask
| #define PWM_RCAPDAT2_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT2: RCAPDAT Position
| #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) |
PWM_T::RCAPDAT3: RCAPDAT Mask
| #define PWM_RCAPDAT3_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT3: RCAPDAT Position
| #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) |
PWM_T::RCAPDAT4: RCAPDAT Mask
| #define PWM_RCAPDAT4_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT4: RCAPDAT Position
| #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) |
PWM_T::RCAPDAT5: RCAPDAT Mask
| #define PWM_RCAPDAT5_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT5: RCAPDAT Position
| #define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) |
PWM_T::SSCTL: SSEN0 Mask
| #define PWM_SSCTL_SSEN0_Pos (0) |
PWM_T::SSCTL: SSEN0 Position
| #define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) |
PWM_T::SSCTL: SSEN1 Mask
| #define PWM_SSCTL_SSEN1_Pos (1) |
PWM_T::SSCTL: SSEN1 Position
| #define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) |
PWM_T::SSCTL: SSEN2 Mask
| #define PWM_SSCTL_SSEN2_Pos (2) |
PWM_T::SSCTL: SSEN2 Position
| #define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) |
PWM_T::SSCTL: SSEN3 Mask
| #define PWM_SSCTL_SSEN3_Pos (3) |
PWM_T::SSCTL: SSEN3 Position
| #define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) |
PWM_T::SSCTL: SSEN4 Mask
| #define PWM_SSCTL_SSEN4_Pos (4) |
PWM_T::SSCTL: SSEN4 Position
| #define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) |
PWM_T::SSCTL: SSEN5 Mask
| #define PWM_SSCTL_SSEN5_Pos (5) |
PWM_T::SSCTL: SSEN5 Position
| #define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) |
PWM_T::SSCTL: SSENn Mask
| #define PWM_SSCTL_SSENn_Pos (0) |
PWM_T::SSCTL: SSENn Position
| #define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) |
PWM_T::SSTRG: CNTSEN Mask
| #define PWM_SSTRG_CNTSEN_Pos (0) |
PWM_T::SSTRG: CNTSEN Position
| #define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) |
PWM_T::STATUS: ADCTRGF0 Mask
| #define PWM_STATUS_ADCTRGF0_Pos (16) |
PWM_T::STATUS: ADCTRGF0 Position
| #define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) |
PWM_T::STATUS: ADCTRGF1 Mask
| #define PWM_STATUS_ADCTRGF1_Pos (17) |
PWM_T::STATUS: ADCTRGF1 Position
| #define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) |
PWM_T::STATUS: ADCTRGF2 Mask
| #define PWM_STATUS_ADCTRGF2_Pos (18) |
PWM_T::STATUS: ADCTRGF2 Position
| #define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) |
PWM_T::STATUS: ADCTRGF3 Mask
| #define PWM_STATUS_ADCTRGF3_Pos (19) |
PWM_T::STATUS: ADCTRGF3 Position
| #define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) |
PWM_T::STATUS: ADCTRGF4 Mask
| #define PWM_STATUS_ADCTRGF4_Pos (20) |
PWM_T::STATUS: ADCTRGF4 Position
| #define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) |
PWM_T::STATUS: ADCTRGF5 Mask
| #define PWM_STATUS_ADCTRGF5_Pos (21) |
PWM_T::STATUS: ADCTRGF5 Position
| #define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) |
PWM_T::STATUS: ADCTRGFn Mask
| #define PWM_STATUS_ADCTRGFn_Pos (16) |
PWM_T::STATUS: ADCTRGFn Position
| #define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) |
PWM_T::STATUS: CNTMAXF0 Mask
| #define PWM_STATUS_CNTMAXF0_Pos (0) |
PWM_T::STATUS: CNTMAXF0 Position
| #define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) |
PWM_T::STATUS: CNTMAXF1 Mask
| #define PWM_STATUS_CNTMAXF1_Pos (1) |
PWM_T::STATUS: CNTMAXF1 Position
| #define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) |
PWM_T::STATUS: CNTMAXF2 Mask
| #define PWM_STATUS_CNTMAXF2_Pos (2) |
PWM_T::STATUS: CNTMAXF2 Position
| #define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) |
PWM_T::STATUS: CNTMAXF3 Mask
| #define PWM_STATUS_CNTMAXF3_Pos (3) |
PWM_T::STATUS: CNTMAXF3 Position
| #define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) |
PWM_T::STATUS: CNTMAXF4 Mask
| #define PWM_STATUS_CNTMAXF4_Pos (4) |
PWM_T::STATUS: CNTMAXF4 Position
| #define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) |
PWM_T::STATUS: CNTMAXF5 Mask
| #define PWM_STATUS_CNTMAXF5_Pos (5) |
PWM_T::STATUS: CNTMAXF5 Position
| #define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) |
PWM_T::STATUS: CNTMAXFn Mask
| #define PWM_STATUS_CNTMAXFn_Pos (0) |
PWM_T::STATUS: CNTMAXFn Position
| #define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) |
PWM_T::STATUS: SYNCINF0 Mask
| #define PWM_STATUS_SYNCINF0_Pos (8) |
PWM_T::STATUS: SYNCINF0 Position
| #define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) |
PWM_T::STATUS: SYNCINF2 Mask
| #define PWM_STATUS_SYNCINF2_Pos (9) |
PWM_T::STATUS: SYNCINF2 Position
| #define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) |
PWM_T::STATUS: SYNCINF4 Mask
| #define PWM_STATUS_SYNCINF4_Pos (10) |
PWM_T::STATUS: SYNCINF4 Position
| #define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) |
PWM_T::STATUS: SYNCINFn Mask
| #define PWM_STATUS_SYNCINFn_Pos (8) |
PWM_T::STATUS: SYNCINFn Position
| #define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) |
PWM_T::SWBRK: BRKETRG0 Mask
| #define PWM_SWBRK_BRKETRG0_Pos (0) |
PWM_T::SWBRK: BRKETRG0 Position
| #define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) |
PWM_T::SWBRK: BRKETRG2 Mask
| #define PWM_SWBRK_BRKETRG2_Pos (1) |
PWM_T::SWBRK: BRKETRG2 Position
| #define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) |
PWM_T::SWBRK: BRKETRG4 Mask
| #define PWM_SWBRK_BRKETRG4_Pos (2) |
PWM_T::SWBRK: BRKETRG4 Position
| #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) |
PWM_T::SWBRK: BRKETRGn Mask
| #define PWM_SWBRK_BRKETRGn_Pos (0) |
PWM_T::SWBRK: BRKETRGn Position
| #define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) |
PWM_T::SWBRK: BRKLTRG0 Mask
| #define PWM_SWBRK_BRKLTRG0_Pos (8) |
PWM_T::SWBRK: BRKLTRG0 Position
| #define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) |
PWM_T::SWBRK: BRKLTRG2 Mask
| #define PWM_SWBRK_BRKLTRG2_Pos (9) |
PWM_T::SWBRK: BRKLTRG2 Position
| #define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) |
PWM_T::SWBRK: BRKLTRG4 Mask
| #define PWM_SWBRK_BRKLTRG4_Pos (10) |
PWM_T::SWBRK: BRKLTRG4 Position
| #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) |
PWM_T::SWBRK: BRKLTRGn Mask
| #define PWM_SWBRK_BRKLTRGn_Pos (8) |
PWM_T::SWBRK: BRKLTRGn Position
| #define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) |
PWM_T::SWSYNC: SWSYNC0 Mask
| #define PWM_SWSYNC_SWSYNC0_Pos (0) |
PWM_T::SWSYNC: SWSYNC0 Position
| #define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) |
PWM_T::SWSYNC: SWSYNC2 Mask
| #define PWM_SWSYNC_SWSYNC2_Pos (1) |
PWM_T::SWSYNC: SWSYNC2 Position
| #define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) |
PWM_T::SWSYNC: SWSYNC4 Mask
| #define PWM_SWSYNC_SWSYNC4_Pos (2) |
PWM_T::SWSYNC: SWSYNC4 Position
| #define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) |
PWM_T::SWSYNC: SWSYNCn Mask
| #define PWM_SWSYNC_SWSYNCn_Pos (0) |
PWM_T::SWSYNC: SWSYNCn Position
| #define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) |
PWM_T::SYNC: PHSDIR0 Mask
| #define PWM_SYNC_PHSDIR0_Pos (24) |
PWM_T::SYNC: PHSDIR0 Position
| #define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) |
PWM_T::SYNC: PHSDIR2 Mask
| #define PWM_SYNC_PHSDIR2_Pos (25) |
PWM_T::SYNC: PHSDIR2 Position
| #define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) |
PWM_T::SYNC: PHSDIR4 Mask
| #define PWM_SYNC_PHSDIR4_Pos (26) |
PWM_T::SYNC: PHSDIR4 Position
| #define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) |
PWM_T::SYNC: PHSDIRn Mask
| #define PWM_SYNC_PHSDIRn_Pos (24) |
PWM_T::SYNC: PHSDIRn Position
| #define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) |
PWM_T::SYNC: PHSEN0 Mask
| #define PWM_SYNC_PHSEN0_Pos (0) |
PWM_T::SYNC: PHSEN0 Position
| #define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) |
PWM_T::SYNC: PHSEN2 Mask
| #define PWM_SYNC_PHSEN2_Pos (1) |
PWM_T::SYNC: PHSEN2 Position
| #define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) |
PWM_T::SYNC: PHSEN4 Mask
| #define PWM_SYNC_PHSEN4_Pos (2) |
PWM_T::SYNC: PHSEN4 Position
| #define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) |
PWM_T::SYNC: PHSENn Mask
| #define PWM_SYNC_PHSENn_Pos (0) |
PWM_T::SYNC: PHSENn Position
| #define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) |
PWM_T::SYNC: SFLTCNT Mask
| #define PWM_SYNC_SFLTCNT_Pos (20) |
PWM_T::SYNC: SFLTCNT Position
| #define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) |
PWM_T::SYNC: SFLTCSEL Mask
| #define PWM_SYNC_SFLTCSEL_Pos (17) |
PWM_T::SYNC: SFLTCSEL Position
| #define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) |
PWM_T::SYNC: SINPINV Mask
| #define PWM_SYNC_SINPINV_Pos (23) |
PWM_T::SYNC: SINPINV Position
| #define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) |
PWM_T::SYNC: SINSRC0 Mask
| #define PWM_SYNC_SINSRC0_Pos (8) |
PWM_T::SYNC: SINSRC0 Position
| #define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) |
PWM_T::SYNC: SINSRC2 Mask
| #define PWM_SYNC_SINSRC2_Pos (10) |
PWM_T::SYNC: SINSRC2 Position
| #define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) |
PWM_T::SYNC: SINSRC4 Mask
| #define PWM_SYNC_SINSRC4_Pos (12) |
PWM_T::SYNC: SINSRC4 Position
| #define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) |
PWM_T::SYNC: SINSRCn Mask
| #define PWM_SYNC_SINSRCn_Pos (8) |
PWM_T::SYNC: SINSRCn Position
| #define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) |
PWM_T::SYNC: SNFLTEN Mask
| #define PWM_SYNC_SNFLTEN_Pos (16) |
PWM_T::SYNC: SNFLTEN Position
| #define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) |
PWM_T::WGCTL0: PRDPCTL0 Mask
| #define PWM_WGCTL0_PRDPCTL0_Pos (16) |
PWM_T::WGCTL0: PRDPCTL0 Position
| #define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) |
PWM_T::WGCTL0: PRDPCTL1 Mask
| #define PWM_WGCTL0_PRDPCTL1_Pos (18) |
PWM_T::WGCTL0: PRDPCTL1 Position
| #define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) |
PWM_T::WGCTL0: PRDPCTL2 Mask
| #define PWM_WGCTL0_PRDPCTL2_Pos (20) |
PWM_T::WGCTL0: PRDPCTL2 Position
| #define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) |
PWM_T::WGCTL0: PRDPCTL3 Mask
| #define PWM_WGCTL0_PRDPCTL3_Pos (22) |
PWM_T::WGCTL0: PRDPCTL3 Position
| #define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) |
PWM_T::WGCTL0: PRDPCTL4 Mask
| #define PWM_WGCTL0_PRDPCTL4_Pos (24) |
PWM_T::WGCTL0: PRDPCTL4 Position
| #define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) |
PWM_T::WGCTL0: PRDPCTL5 Mask
| #define PWM_WGCTL0_PRDPCTL5_Pos (26) |
PWM_T::WGCTL0: PRDPCTL5 Position
| #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) |
PWM_T::WGCTL0: PRDPCTLn Mask
| #define PWM_WGCTL0_PRDPCTLn_Pos (16) |
PWM_T::WGCTL0: PRDPCTLn Position
| #define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) |
PWM_T::WGCTL0: ZPCTL0 Mask
| #define PWM_WGCTL0_ZPCTL0_Pos (0) |
PWM_T::WGCTL0: ZPCTL0 Position
| #define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) |
PWM_T::WGCTL0: ZPCTL1 Mask
| #define PWM_WGCTL0_ZPCTL1_Pos (2) |
PWM_T::WGCTL0: ZPCTL1 Position
| #define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) |
PWM_T::WGCTL0: ZPCTL2 Mask
| #define PWM_WGCTL0_ZPCTL2_Pos (4) |
PWM_T::WGCTL0: ZPCTL2 Position
| #define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) |
PWM_T::WGCTL0: ZPCTL3 Mask
| #define PWM_WGCTL0_ZPCTL3_Pos (6) |
PWM_T::WGCTL0: ZPCTL3 Position
| #define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) |
PWM_T::WGCTL0: ZPCTL4 Mask
| #define PWM_WGCTL0_ZPCTL4_Pos (8) |
PWM_T::WGCTL0: ZPCTL4 Position
| #define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) |
PWM_T::WGCTL0: ZPCTL5 Mask
| #define PWM_WGCTL0_ZPCTL5_Pos (10) |
PWM_T::WGCTL0: ZPCTL5 Position
| #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) |
PWM_T::WGCTL0: ZPCTLn Mask
| #define PWM_WGCTL0_ZPCTLn_Pos (0) |
PWM_T::WGCTL0: ZPCTLn Position
| #define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) |
PWM_T::WGCTL1: CMPDCTL0 Mask
| #define PWM_WGCTL1_CMPDCTL0_Pos (16) |
PWM_T::WGCTL1: CMPDCTL0 Position
| #define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) |
PWM_T::WGCTL1: CMPDCTL1 Mask
| #define PWM_WGCTL1_CMPDCTL1_Pos (18) |
PWM_T::WGCTL1: CMPDCTL1 Position
| #define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) |
PWM_T::WGCTL1: CMPDCTL2 Mask
| #define PWM_WGCTL1_CMPDCTL2_Pos (20) |
PWM_T::WGCTL1: CMPDCTL2 Position
| #define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) |
PWM_T::WGCTL1: CMPDCTL3 Mask
| #define PWM_WGCTL1_CMPDCTL3_Pos (22) |
PWM_T::WGCTL1: CMPDCTL3 Position
| #define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) |
PWM_T::WGCTL1: CMPDCTL4 Mask
| #define PWM_WGCTL1_CMPDCTL4_Pos (24) |
PWM_T::WGCTL1: CMPDCTL4 Position
| #define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) |
PWM_T::WGCTL1: CMPDCTL5 Mask
| #define PWM_WGCTL1_CMPDCTL5_Pos (26) |
PWM_T::WGCTL1: CMPDCTL5 Position
| #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) |
PWM_T::WGCTL1: CMPDCTLn Mask
| #define PWM_WGCTL1_CMPDCTLn_Pos (16) |
PWM_T::WGCTL1: CMPDCTLn Position
| #define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) |
PWM_T::WGCTL1: CMPUCTL0 Mask
| #define PWM_WGCTL1_CMPUCTL0_Pos (0) |
PWM_T::WGCTL1: CMPUCTL0 Position
| #define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) |
PWM_T::WGCTL1: CMPUCTL1 Mask
| #define PWM_WGCTL1_CMPUCTL1_Pos (2) |
PWM_T::WGCTL1: CMPUCTL1 Position
| #define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) |
PWM_T::WGCTL1: CMPUCTL2 Mask
| #define PWM_WGCTL1_CMPUCTL2_Pos (4) |
PWM_T::WGCTL1: CMPUCTL2 Position
| #define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) |
PWM_T::WGCTL1: CMPUCTL3 Mask
| #define PWM_WGCTL1_CMPUCTL3_Pos (6) |
PWM_T::WGCTL1: CMPUCTL3 Position
| #define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) |
PWM_T::WGCTL1: CMPUCTL4 Mask
| #define PWM_WGCTL1_CMPUCTL4_Pos (8) |
PWM_T::WGCTL1: CMPUCTL4 Position
| #define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) |
PWM_T::WGCTL1: CMPUCTL5 Mask
| #define PWM_WGCTL1_CMPUCTL5_Pos (10) |
PWM_T::WGCTL1: CMPUCTL5 Position
| #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) |
PWM_T::WGCTL1: CMPUCTLn Mask
| #define PWM_WGCTL1_CMPUCTLn_Pos (0) |
PWM_T::WGCTL1: CMPUCTLn Position
| #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
RTC_T::CAL: DAY Mask
| #define RTC_CAL_DAY_Pos (0) |
RTC_T::CAL: DAY Position
| #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
RTC_T::CAL: MON Mask
| #define RTC_CAL_MON_Pos (8) |
RTC_T::CAL: MON Position
| #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
RTC_T::CAL: TENDAY Mask
| #define RTC_CAL_TENDAY_Pos (4) |
RTC_T::CAL: TENDAY Position
| #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
RTC_T::CAL: TENMON Mask
| #define RTC_CAL_TENMON_Pos (12) |
RTC_T::CAL: TENMON Position
| #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
RTC_T::CAL: TENYEAR Mask
| #define RTC_CAL_TENYEAR_Pos (20) |
RTC_T::CAL: TENYEAR Position
| #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
RTC_T::CAL: YEAR Mask
| #define RTC_CAL_YEAR_Pos (16) |
RTC_T::CAL: YEAR Position
| #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
RTC_T::CALM: DAY Mask
| #define RTC_CALM_DAY_Pos (0) |
RTC_T::CALM: DAY Position
| #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
RTC_T::CALM: MON Mask
| #define RTC_CALM_MON_Pos (8) |
RTC_T::CALM: MON Position
| #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
RTC_T::CALM: TENDAY Mask
| #define RTC_CALM_TENDAY_Pos (4) |
RTC_T::CALM: TENDAY Position
| #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
RTC_T::CALM: TENMON Mask
| #define RTC_CALM_TENMON_Pos (12) |
RTC_T::CALM: TENMON Position
| #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
RTC_T::CALM: TENYEAR Mask
| #define RTC_CALM_TENYEAR_Pos (20) |
RTC_T::CALM: TENYEAR Position
| #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
RTC_T::CALM: YEAR Mask
| #define RTC_CALM_YEAR_Pos (16) |
RTC_T::CALM: YEAR Position
| #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
RTC_T::CAMSK: MDAY Mask
| #define RTC_CAMSK_MDAY_Pos (0) |
RTC_T::CAMSK: MDAY Position
| #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
RTC_T::CAMSK: MMON Mask
| #define RTC_CAMSK_MMON_Pos (2) |
RTC_T::CAMSK: MMON Position
| #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
RTC_T::CAMSK: MTENDAY Mask
| #define RTC_CAMSK_MTENDAY_Pos (1) |
RTC_T::CAMSK: MTENDAY Position
| #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
RTC_T::CAMSK: MTENMON Mask
| #define RTC_CAMSK_MTENMON_Pos (3) |
RTC_T::CAMSK: MTENMON Position
| #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
RTC_T::CAMSK: MTENYEAR Mask
| #define RTC_CAMSK_MTENYEAR_Pos (5) |
RTC_T::CAMSK: MTENYEAR Position
| #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
RTC_T::CAMSK: MYEAR Mask
| #define RTC_CAMSK_MYEAR_Pos (4) |
RTC_T::CAMSK: MYEAR Position
| #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
RTC_T::CLKFMT: 24HEN Mask
| #define RTC_CLKFMT_24HEN_Pos (0) |
RTC_T::CLKFMT: 24HEN Position
| #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) |
RTC_T::FREQADJ: FRACTION Mask
| #define RTC_FREQADJ_FRACTION_Pos (0) |
RTC_T::FREQADJ: FRACTION Position
| #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) |
RTC_T::FREQADJ: INTEGER Mask
| #define RTC_FREQADJ_INTEGER_Pos (8) |
RTC_T::FREQADJ: INTEGER Position
| #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) |
RTC_T::INIT: ACTIVE Mask
| #define RTC_INIT_ACTIVE_Pos (0) |
@addtogroup RTC_CONST RTC Bit Field Definition Constant Definitions for RTC Controller
RTC_T::INIT: ACTIVE Position
| #define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) |
RTC_T::INIT: INIT Mask
| #define RTC_INIT_INIT_Pos (0) |
RTC_T::INIT: INIT Position
| #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
RTC_T::INTEN: ALMIEN Mask
| #define RTC_INTEN_ALMIEN_Pos (0) |
RTC_T::INTEN: ALMIEN Position
| #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) |
RTC_T::INTEN: SNPDIEN Mask
| #define RTC_INTEN_SNPDIEN_Pos (2) |
RTC_T::INTEN: SNPDIEN Position
| #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
RTC_T::INTEN: TICKIEN Mask
| #define RTC_INTEN_TICKIEN_Pos (1) |
RTC_T::INTEN: TICKIEN Position
| #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
RTC_T::INTSTS: ALMIF Mask
| #define RTC_INTSTS_ALMIF_Pos (0) |
RTC_T::INTSTS: ALMIF Position
| #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) |
RTC_T::INTSTS: SNPDIF Mask
| #define RTC_INTSTS_SNPDIF_Pos (2) |
RTC_T::INTSTS: SNPDIF Position
| #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
RTC_T::INTSTS: TICKIF Mask
| #define RTC_INTSTS_TICKIF_Pos (1) |
RTC_T::INTSTS: TICKIF Position
| #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
RTC_T::LEAPYEAR: LEAPYEAR Mask
| #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
RTC_T::LEAPYEAR: LEAPYEAR Position
| #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) |
RTC_T::LXTCTL: GAIN Mask
| #define RTC_LXTCTL_GAIN_Pos (1) |
RTC_T::LXTCTL: GAIN Position
| #define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) |
RTC_T::LXTCTL: LXTEN Mask
| #define RTC_LXTCTL_LXTEN_Pos (0) |
RTC_T::LXTCTL: LXTEN Position
| #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) |
RTC_T::LXTICTL: CTLSEL Mask
| #define RTC_LXTICTL_CTLSEL_Pos (3) |
RTC_T::LXTICTL: CTLSEL Position
| #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) |
RTC_T::LXTICTL: DOUT Mask
| #define RTC_LXTICTL_DOUT_Pos (2) |
RTC_T::LXTICTL: DOUT Position
| #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) |
RTC_T::LXTICTL: OPMODE Mask
| #define RTC_LXTICTL_OPMODE_Pos (0) |
RTC_T::LXTICTL: OPMODE Position
| #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) |
RTC_T::LXTOCTL: CTLSEL Mask
| #define RTC_LXTOCTL_CTLSEL_Pos (3) |
RTC_T::LXTOCTL: CTLSEL Position
| #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) |
RTC_T::LXTOCTL: DOUT Mask
| #define RTC_LXTOCTL_DOUT_Pos (2) |
RTC_T::LXTOCTL: DOUT Position
| #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) |
RTC_T::LXTOCTL: OPMODE Mask
| #define RTC_LXTOCTL_OPMODE_Pos (0) |
RTC_T::LXTOCTL: OPMODE Position
| #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) |
RTC_T::RWEN: RWEN Mask
| #define RTC_RWEN_RWEN_Pos (0) |
RTC_T::RWEN: RWEN Position
| #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
RTC_T::RWEN: RWENF Mask
| #define RTC_RWEN_RWENF_Pos (16) |
RTC_T::RWEN: RWENF Position
| #define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) |
RTC_T::SPR: SPARE Mask
| #define RTC_SPR_SPARE_Pos (0) |
RTC_T::SPR: SPARE Position
| #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) |
RTC_T::SPRCTL: SNPDEN Mask
| #define RTC_SPRCTL_SNPDEN_Pos (0) |
RTC_T::SPRCTL: SNPDEN Position
| #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) |
RTC_T::SPRCTL: SNPTYPE0 Mask
| #define RTC_SPRCTL_SNPTYPE0_Pos (1) |
RTC_T::SPRCTL: SNPTYPE0 Position
| #define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) |
RTC_T::SPRCTL: SNPTYPE1 Mask
| #define RTC_SPRCTL_SNPTYPE1_Pos (3) |
RTC_T::SPRCTL: SNPTYPE1 Position
| #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) |
RTC_T::SPRCTL: SPRCSTS Mask
| #define RTC_SPRCTL_SPRCSTS_Pos (5) |
RTC_T::SPRCTL: SPRCSTS Position
| #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) |
RTC_T::SPRCTL: SPRRWEN Mask
| #define RTC_SPRCTL_SPRRWEN_Pos (2) |
RTC_T::SPRCTL: SPRRWEN Position
| #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) |
RTC_T::SPRCTL: SPRRWRDY Mask
| #define RTC_SPRCTL_SPRRWRDY_Pos (7) |
RTC_T::SPRCTL: SPRRWRDY Position
| #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
RTC_T::TALM: HR Mask
| #define RTC_TALM_HR_Pos (16) |
RTC_T::TALM: HR Position
| #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
RTC_T::TALM: MIN Mask
| #define RTC_TALM_MIN_Pos (8) |
RTC_T::TALM: MIN Position
| #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
RTC_T::TALM: SEC Mask
| #define RTC_TALM_SEC_Pos (0) |
RTC_T::TALM: SEC Position
| #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
RTC_T::TALM: TENHR Mask
| #define RTC_TALM_TENHR_Pos (20) |
RTC_T::TALM: TENHR Position
| #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
RTC_T::TALM: TENMIN Mask
| #define RTC_TALM_TENMIN_Pos (12) |
RTC_T::TALM: TENMIN Position
| #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
RTC_T::TALM: TENSEC Mask
| #define RTC_TALM_TENSEC_Pos (4) |
RTC_T::TALM: TENSEC Position
| #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) |
RTC_T::TAMPCTL: CTLSEL Mask
| #define RTC_TAMPCTL_CTLSEL_Pos (3) |
RTC_T::TAMPCTL: CTLSEL Position
| #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) |
RTC_T::TAMPCTL: DOUT Mask
| #define RTC_TAMPCTL_DOUT_Pos (2) |
RTC_T::TAMPCTL: DOUT Position
| #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) |
RTC_T::TAMPCTL: OPMODE Mask
| #define RTC_TAMPCTL_OPMODE_Pos (0) |
RTC_T::TAMPCTL: OPMODE Position
| #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
RTC_T::TAMSK: MHR Mask
| #define RTC_TAMSK_MHR_Pos (4) |
RTC_T::TAMSK: MHR Position
| #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
RTC_T::TAMSK: MMIN Mask
| #define RTC_TAMSK_MMIN_Pos (2) |
RTC_T::TAMSK: MMIN Position
| #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
RTC_T::TAMSK: MSEC Mask
| #define RTC_TAMSK_MSEC_Pos (0) |
RTC_T::TAMSK: MSEC Position
| #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
RTC_T::TAMSK: MTENHR Mask
| #define RTC_TAMSK_MTENHR_Pos (5) |
RTC_T::TAMSK: MTENHR Position
| #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
RTC_T::TAMSK: MTENMIN Mask
| #define RTC_TAMSK_MTENMIN_Pos (3) |
RTC_T::TAMSK: MTENMIN Position
| #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
RTC_T::TAMSK: MTENSEC Mask
| #define RTC_TAMSK_MTENSEC_Pos (1) |
RTC_T::TAMSK: MTENSEC Position
| #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) |
RTC_T::TICK: TICK Mask
| #define RTC_TICK_TICK_Pos (0) |
RTC_T::TICK: TICK Position
| #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
RTC_T::TIME: HR Mask
| #define RTC_TIME_HR_Pos (16) |
RTC_T::TIME: HR Position
| #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
RTC_T::TIME: MIN Mask
| #define RTC_TIME_MIN_Pos (8) |
RTC_T::TIME: MIN Position
| #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
RTC_T::TIME: SEC Mask
| #define RTC_TIME_SEC_Pos (0) |
RTC_T::TIME: SEC Position
| #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
RTC_T::TIME: TENHR Mask
| #define RTC_TIME_TENHR_Pos (20) |
RTC_T::TIME: TENHR Position
| #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
RTC_T::TIME: TENMIN Mask
| #define RTC_TIME_TENMIN_Pos (12) |
RTC_T::TIME: TENMIN Position
| #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
RTC_T::TIME: TENSEC Mask
| #define RTC_TIME_TENSEC_Pos (4) |
RTC_T::TIME: TENSEC Position
| #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
RTC_T::WEEKDAY: WEEKDAY Mask
| #define RTC_WEEKDAY_WEEKDAY_Pos (0) |
RTC_T::WEEKDAY: WEEKDAY Position
| #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
SC_T::ALTCTL: ACTEN Mask
| #define SC_ALTCTL_ACTEN_Pos (3) |
SC_T::ALTCTL: ACTEN Position
| #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
SC_T::ALTCTL: ACTSTS0 Mask
| #define SC_ALTCTL_ACTSTS0_Pos (13) |
SC_T::ALTCTL: ACTSTS0 Position
| #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
SC_T::ALTCTL: ACTSTS1 Mask
| #define SC_ALTCTL_ACTSTS1_Pos (14) |
SC_T::ALTCTL: ACTSTS1 Position
| #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
SC_T::ALTCTL: ACTSTS2 Mask
| #define SC_ALTCTL_ACTSTS2_Pos (15) |
SC_T::ALTCTL: ACTSTS2 Position
| #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) |
SC_T::ALTCTL: ADACEN Mask
| #define SC_ALTCTL_ADACEN_Pos (11) |
SC_T::ALTCTL: ADACEN Position
| #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
SC_T::ALTCTL: CNTEN0 Mask
| #define SC_ALTCTL_CNTEN0_Pos (5) |
SC_T::ALTCTL: CNTEN0 Position
| #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
SC_T::ALTCTL: CNTEN1 Mask
| #define SC_ALTCTL_CNTEN1_Pos (6) |
SC_T::ALTCTL: CNTEN1 Position
| #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
SC_T::ALTCTL: CNTEN2 Mask
| #define SC_ALTCTL_CNTEN2_Pos (7) |
SC_T::ALTCTL: CNTEN2 Position
| #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
SC_T::ALTCTL: DACTEN Mask
| #define SC_ALTCTL_DACTEN_Pos (2) |
SC_T::ALTCTL: DACTEN Position
| #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
SC_T::ALTCTL: INITSEL Mask
| #define SC_ALTCTL_INITSEL_Pos (8) |
SC_T::ALTCTL: INITSEL Position
| #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) |
SC_T::ALTCTL: OUTSEL Mask
| #define SC_ALTCTL_OUTSEL_Pos (16) |
SC_T::ALTCTL: OUTSEL Position
| #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
SC_T::ALTCTL: RXBGTEN Mask
| #define SC_ALTCTL_RXBGTEN_Pos (12) |
SC_T::ALTCTL: RXBGTEN Position
| #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
SC_T::ALTCTL: RXRST Mask
| #define SC_ALTCTL_RXRST_Pos (1) |
SC_T::ALTCTL: RXRST Position
| #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
SC_T::ALTCTL: TXRST Mask
| #define SC_ALTCTL_TXRST_Pos (0) |
SC_T::ALTCTL: TXRST Position
| #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
SC_T::ALTCTL: WARSTEN Mask
| #define SC_ALTCTL_WARSTEN_Pos (4) |
SC_T::ALTCTL: WARSTEN Position
| #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
| #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
| #define SC_CTL_CDDBSEL_Pos (24) |
| #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) |
| #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
| #define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) |
| #define SC_CTL_ICEDEBUG_Pos (31) |
| #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
| #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
| #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
| #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
| #define SC_CTL_RXRTYEN_Pos (19) |
| #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
| #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
| #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
| #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
| #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
| #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
| #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
| #define SC_CTL_TXRTYEN_Pos (23) |
| #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define SC_DAT_DAT_Pos (0) |
| #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
| #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) |
SC_T::ETUCTL: CMPEN_ Mask
| #define SC_ETUCTL_CMPEN_Pos (15) |
SC_T::ETUCTL: CMPEN_ Position
| #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
SC_T::ETUCTL: ETURDIV_ Mask
| #define SC_ETUCTL_ETURDIV_Pos (0) |
SC_T::ETUCTL: ETURDIV_ Position
| #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
SC_T::INTEN: ACERRIEN Mask
| #define SC_INTEN_ACERRIEN_Pos (10) |
SC_T::INTEN: ACERRIEN Position
| #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
SC_T::INTEN: BGTIEN Mask
| #define SC_INTEN_BGTIEN_Pos (6) |
SC_T::INTEN: BGTIEN Position
| #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
SC_T::INTEN: CDIEN Mask
| #define SC_INTEN_CDIEN_Pos (7) |
SC_T::INTEN: CDIEN Position
| #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
SC_T::INTEN: INITIEN Mask
| #define SC_INTEN_INITIEN_Pos (8) |
SC_T::INTEN: INITIEN Position
| #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
SC_T::INTEN: RDAIEN Mask
| #define SC_INTEN_RDAIEN_Pos (0) |
SC_T::INTEN: RDAIEN Position
| #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) |
SC_T::INTEN: RXTOIF Mask
| #define SC_INTEN_RXTOIF_Pos (9) |
SC_T::INTEN: RXTOIF Position
| #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
SC_T::INTEN: TBEIEN Mask
| #define SC_INTEN_TBEIEN_Pos (1) |
SC_T::INTEN: TBEIEN Position
| #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
SC_T::INTEN: TERRIEN Mask
| #define SC_INTEN_TERRIEN_Pos (2) |
SC_T::INTEN: TERRIEN Position
| #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
SC_T::INTEN: TMR0IEN Mask
| #define SC_INTEN_TMR0IEN_Pos (3) |
SC_T::INTEN: TMR0IEN_Position
| #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
SC_T::INTEN: TMR1IEN Mask
| #define SC_INTEN_TMR1IEN_Pos (4) |
SC_T::INTEN: TMR1IEN Position
| #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
SC_T::INTEN: TMR2IEN Mask
| #define SC_INTEN_TMR2IEN_Pos (5) |
SC_T::INTEN: TMR2IEN Position
| #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
SC_T::INTSTS: ACERRIF Mask
| #define SC_INTSTS_ACERRIF_Pos (10) |
SC_T::INTSTS: ACERRIF Position
| #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
SC_T::INTSTS: BGTIF Mask
| #define SC_INTSTS_BGTIF_Pos (6) |
SC_T::INTSTS: BGTIF Position
| #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
SC_T::INTSTS: CDIF Mask
| #define SC_INTSTS_CDIF_Pos (7) |
SC_T::INTSTS: CDIF Position
| #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
SC_T::INTSTS: INITIF Mask
| #define SC_INTSTS_INITIF_Pos (8) |
SC_T::INTSTS: INITIF Position
| #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) |
SC_T::INTSTS: RBTOIF Mask
| #define SC_INTSTS_RBTOIF_Pos (9) |
SC_T::INTSTS: RBTOIF Position
| #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
SC_T::INTSTS: RDAIF Mask
| #define SC_INTSTS_RDAIF_Pos (0) |
SC_T::INTSTS: RDAIF Position
| #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
SC_T::INTSTS: TBEIF Mask
| #define SC_INTSTS_TBEIF_Pos (1) |
SC_T::INTSTS: TBEIF Position
| #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
SC_T::INTSTS: TERRIF Mask
| #define SC_INTSTS_TERRIF_Pos (2) |
SC_T::INTSTS: TERRIF Position
| #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
SC_T::INTSTS: TMR0IF Mask
| #define SC_INTSTS_TMR0IF_Pos (3) |
SC_T::INTSTS: TMR0IF Position
| #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
SC_T::INTSTS: TMR1IF Mask
| #define SC_INTSTS_TMR1IF_Pos (4) |
SC_T::INTSTS: TMR1IF Position
| #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
SC_T::INTSTS: TMR2IF Mask
| #define SC_INTSTS_TMR2IF_Pos (5) |
SC_T::INTSTS: TMR2IF Position
| #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
SC_T::PINCTL: CLKKEEP Msk
| #define SC_PINCTL_CLKKEEP_Pos (6) |
SC_T::PINCTL: CLKKEEP Position
| #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) |
SC_T::PINCTL: CSTOPLV Msk
| #define SC_PINCTL_CSTOPLV_Pos (5) |
SC_T::PINCTL: CSTOPLV Position
| #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) |
SC_T::PINCTL: DATSTS Msk
| #define SC_PINCTL_DATSTS_Pos (16) |
SC_T::PINCTL: DATSTS Position
| #define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) |
SC_T::PINCTL: LOOPBK Msk
| #define SC_PINCTL_LOOPBK_Pos (31) |
SC_T::PINCTL: LOOPBK Position
| #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
SC_T::PINCTL: PWREN Msk
| #define SC_PINCTL_PWREN_Pos (0) |
SC_T::PINCTL: PWREN Position
| #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
SC_T::PINCTL: PWRINV Msk
| #define SC_PINCTL_PWRINV_Pos (11) |
SC_T::PINCTL: PWRINV Position
| #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) |
SC_T::PINCTL: PWRSTS Msk
| #define SC_PINCTL_PWRSTS_Pos (17) |
SC_T::PINCTL: PWRSTS Position
| #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) |
SC_T::PINCTL: RSTSTS Msk
| #define SC_PINCTL_RSTSTS_Pos (18) |
SC_T::PINCTL: RSTSTS Position
| #define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) |
SC_T::PINCTL: SCDOSTS Msk
| #define SC_PINCTL_SCDOSTS_Pos (12) |
SC_T::PINCTL: SCDOSTS Position
| #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) |
SC_T::PINCTL: SCDOUT Msk
| #define SC_PINCTL_SCDOUT_Pos (9) |
SC_T::PINCTL: SCDOUT Position
| #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) |
SC_T::PINCTL: SCRST Msk
| #define SC_PINCTL_SCRST_Pos (1) |
SC_T::PINCTL: SCRST Position
| #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
SC_T::PINCTL: SYNC Msk
| #define SC_PINCTL_SYNC_Pos (30) |
SC_T::PINCTL: SYNC Position
| #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
SC_T::RXTOUT: RFTM Mask
| #define SC_RXTOUT_RFTM_Pos (0) |
SC_T::RXTOUT: RFTM Position
| #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
SC_T::STATUS: BEF Mask
| #define SC_STATUS_BEF_Pos (6) |
SC_T::STATUS: BEF Position
| #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) |
SC_T::STATUS: CDPINSTS Mask
| #define SC_STATUS_CDPINSTS_Pos (13) |
SC_T::STATUS: CDPINSTS Position
| #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) |
SC_T::STATUS: CINSERT Mask
| #define SC_STATUS_CINSERT_Pos (12) |
SC_T::STATUS: CINSERT Position
| #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) |
SC_T::STATUS: CREMOVE Mask
| #define SC_STATUS_CREMOVE_Pos (11) |
SC_T::STATUS: CREMOVE Position
| #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
SC_T::STATUS: FEF Mask
| #define SC_STATUS_FEF_Pos (5) |
SC_T::STATUS: FEF Position
| #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
SC_T::STATUS: PEF Mask
| #define SC_STATUS_PEF_Pos (4) |
SC_T::STATUS: PEF Position
| #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
SC_T::STATUS: RXACT Msk
| #define SC_STATUS_RXACT_Pos (23) |
SC_T::STATUS: RXACT Position
| #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
SC_T::STATUS: RXEMPTY Mask
| #define SC_STATUS_RXEMPTY_Pos (1) |
SC_T::STATUS: RXEMPTY Position
| #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
SC_T::STATUS: RXFULL Mask
| #define SC_STATUS_RXFULL_Pos (2) |
SC_T::STATUS: RXFULL Position
| #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
SC_T::STATUS: RXO Mask
| #define SC_STATUS_RXOV_Pos (0) |
SC_T::STATUS: RXO Position
| #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
SC_T::STATUS: RXOVERR Mask
| #define SC_STATUS_RXOVERR_Pos (22) |
SC_T::STATUS: RXOVERR Position
| #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) |
SC_T::STATUS: RXPOINT Mask
| #define SC_STATUS_RXPOINT_Pos (16) |
SC_T::STATUS: RXPOINT Position
| #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
SC_T::STATUS: RXRERR Mask
| #define SC_STATUS_RXRERR_Pos (21) |
SC_T::STATUS: RXRERR Position
| #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
SC_T::STATUS: TXACT Msk
| #define SC_STATUS_TXACT_Pos (31) |
SC_T::STATUS: TXACT Position
| #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
SC_T::STATUS: TXEMPTY Mask
| #define SC_STATUS_TXEMPTY_Pos (9) |
SC_T::STATUS: TXEMPTY Position
| #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
SC_T::STATUS: TXFULL Mask
| #define SC_STATUS_TXFULL_Pos (10) |
SC_T::STATUS: TXFULL Position
| #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
SC_T::STATUS: TXOV Mask
| #define SC_STATUS_TXOV_Pos (8) |
SC_T::STATUS: TXOV Position
| #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
SC_T::STATUS: TXOVERR_ Msk
| #define SC_STATUS_TXOVERR_Pos (30) |
SC_T::STATUS: TXOVERR_ Position
| #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) |
SC_T::STATUS: TXPOINT Msk
| #define SC_STATUS_TXPOINT_Pos (24) |
SC_T::STATUS: TXPOINT Position
| #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
SC_T::STATUS: TXRERR Msk
| #define SC_STATUS_TXRERR_Pos (29) |
SC_T::STATUS: TXRERR Position
| #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
SC_T::TMRCTL0: CNT Msk
| #define SC_TMRCTL0_CNT_Pos (0) |
SC_T::TMRCTL0: CNT Position
| #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
SC_T::TMRCTL0: OPMODE Msk
| #define SC_TMRCTL0_OPMODE_Pos (24) |
SC_T::TMRCTL0: OPMODE Position
| #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
SC_T::TMRCTL1: CNT Msk
| #define SC_TMRCTL1_CNT_Pos (0) |
SC_T::TMRCTL1: CNT Position
| #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
SC_T::TMRCTL1: OPMODE Msk
| #define SC_TMRCTL1_OPMODE_Pos (24) |
SC_T::TMRCTL1: OPMODE Position
| #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
SC_T::TMRCTL2: CNT Msk
| #define SC_TMRCTL2_CNT_Pos (0) |
SC_T::TMRCTL2: CNT Position
| #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
SC_T::TMRCTL2: OPMODE Msk
| #define SC_TMRCTL2_OPMODE_Pos (24) |
SC_T::TMRCTL2: OPMODE Position
| #define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) |
SC_T::TMRDAT0: CNT0 Msk
| #define SC_TMRDAT0_CNT0_Pos (0) |
SC_T::TMRDAT0: CNT0 Position
| #define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) |
SC_T::TMRDAT1_2: CNT1 Msk
| #define SC_TMRDAT1_2_CNT1_Pos (0) |
SC_T::TMRDAT1_2: CNT1 Position
| #define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) |
SC_T::TMRDAT1_2: CNT2 Msk
| #define SC_TMRDAT1_2_CNT2_Pos (8) |
SC_T::TMRDAT1_2: CNT2 Position
| #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
SC_T::UARTCTL: OPE Msk
| #define SC_UARTCTL_OPE_Pos (7) |
SC_T::UARTCTL: OPE Position
| #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
SC_T::UARTCTL: PBOFF Msk
| #define SC_UARTCTL_PBOFF_Pos (6) |
SC_T::UARTCTL: PBOFF Position
| #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
SC_T::UARTCTL: UARTEN Msk
| #define SC_UARTCTL_UARTEN_Pos (0) |
SC_T::UARTCTL: UARTEN Position
| #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) |
SC_T::UARTCTL: WLS Msk
| #define SC_UARTCTL_WLS_Pos (4) |
SC_T::UARTCTL: WLS Position
| #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) |
SPI_T::CLKDIV: DIVIDER Mask
| #define SPI_CLKDIV_DIVIDER_Pos (0) |
SPI_T::CLKDIV: DIVIDER Position
| #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
SPI_T::CTL: CLKPOL Mask
| #define SPI_CTL_CLKPOL_Pos (3) |
SPI_T::CTL: CLKPOL Position
| #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) |
SPI_T::CTL: DUALIOEN Mask
| #define SPI_CTL_DUALIOEN_Pos (21) |
SPI_T::CTL: DUALIOEN Position
| #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
SPI_T::CTL: DWIDTH Mask
| #define SPI_CTL_DWIDTH_Pos (8) |
SPI_T::CTL: DWIDTH Position
| #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
SPI_T::CTL: LSB Mask
| #define SPI_CTL_LSB_Pos (13) |
SPI_T::CTL: LSB Position
| #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) |
SPI_T::CTL: QDIODIR Mask
| #define SPI_CTL_QDIODIR_Pos (20) |
SPI_T::CTL: QDIODIR Position
| #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) |
SPI_T::CTL: QUADIOEN Mask
| #define SPI_CTL_QUADIOEN_Pos (22) |
SPI_T::CTL: QUADIOEN Position
| #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
SPI_T::CTL: REORDER Mask
| #define SPI_CTL_REORDER_Pos (19) |
SPI_T::CTL: REORDER Position
| #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
SPI_T::CTL: RXNEG Mask
| #define SPI_CTL_RXNEG_Pos (1) |
SPI_T::CTL: RXNEG Position
| #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
SPI_T::CTL: SLAVE Mask
| #define SPI_CTL_SLAVE_Pos (18) |
SPI_T::CTL: SLAVE Position
| #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) |
SPI_T::CTL: SPIEN Mask
| #define SPI_CTL_SPIEN_Pos (0) |
@addtogroup SPI_CONST SPI Bit Field Definition Constant Definitions for SPI Controller
SPI_T::CTL: SPIEN Position
| #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
SPI_T::CTL: SUSPITV Mask
| #define SPI_CTL_SUSPITV_Pos (4) |
SPI_T::CTL: SUSPITV Position
| #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) |
SPI_T::CTL: TWOBIT Mask
| #define SPI_CTL_TWOBIT_Pos (16) |
SPI_T::CTL: TWOBIT Position
| #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
SPI_T::CTL: TXNEG Mask
| #define SPI_CTL_TXNEG_Pos (2) |
SPI_T::CTL: TXNEG Position
| #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
SPI_T::CTL: UNITIEN Mask
| #define SPI_CTL_UNITIEN_Pos (17) |
SPI_T::CTL: UNITIEN Position
| #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) |
SPI_T::FIFOCTL: RXFBCLR Mask
| #define SPI_FIFOCTL_RXFBCLR_Pos (8) |
SPI_T::FIFOCTL: RXFBCLR Position
| #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
SPI_T::FIFOCTL: RXOVIEN Mask
| #define SPI_FIFOCTL_RXOVIEN_Pos (5) |
SPI_T::FIFOCTL: RXOVIEN Position
| #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) |
SPI_T::FIFOCTL: RXRST Mask
| #define SPI_FIFOCTL_RXRST_Pos (0) |
SPI_T::FIFOCTL: RXRST Position
| #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
SPI_T::FIFOCTL: RXTH Mask
| #define SPI_FIFOCTL_RXTH_Pos (24) |
SPI_T::FIFOCTL: RXTH Position
| #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
SPI_T::FIFOCTL: RXTHIEN Mask
| #define SPI_FIFOCTL_RXTHIEN_Pos (2) |
SPI_T::FIFOCTL: RXTHIEN Position
| #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
SPI_T::FIFOCTL: RXTOIEN Mask
| #define SPI_FIFOCTL_RXTOIEN_Pos (4) |
SPI_T::FIFOCTL: RXTOIEN Position
| #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) |
SPI_T::FIFOCTL: TXFBCLR Mask
| #define SPI_FIFOCTL_TXFBCLR_Pos (9) |
SPI_T::FIFOCTL: TXFBCLR Position
| #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) |
SPI_T::FIFOCTL: TXRST Mask
| #define SPI_FIFOCTL_TXRST_Pos (1) |
SPI_T::FIFOCTL: TXRST Position
| #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
SPI_T::FIFOCTL: TXTH Mask
| #define SPI_FIFOCTL_TXTH_Pos (28) |
SPI_T::FIFOCTL: TXTH Position
| #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
SPI_T::FIFOCTL: TXTHIEN Mask
| #define SPI_FIFOCTL_TXTHIEN_Pos (3) |
SPI_T::FIFOCTL: TXTHIEN Position
| #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) |
SPI_T::FIFOCTL: TXUFIEN Mask
| #define SPI_FIFOCTL_TXUFIEN_Pos (7) |
SPI_T::FIFOCTL: TXUFIEN Position
| #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) |
SPI_T::FIFOCTL: TXUFPOL Mask
| #define SPI_FIFOCTL_TXUFPOL_Pos (6) |
SPI_T::FIFOCTL: TXUFPOL Position
| #define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) |
SPI_T::I2SCLK: BCLKDIV Mask
| #define SPI_I2SCLK_BCLKDIV_Pos (8) |
SPI_T::I2SCLK: BCLKDIV Position
| #define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) |
SPI_T::I2SCLK: MCLKDIV Mask
| #define SPI_I2SCLK_MCLKDIV_Pos (0) |
SPI_T::I2SCLK: MCLKDIV Position
| #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) |
SPI_T::I2SCTL: FORMAT Mask
| #define SPI_I2SCTL_FORMAT_Pos (28) |
SPI_T::I2SCTL: FORMAT Position
| #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) |
SPI_T::I2SCTL: I2SEN Mask
| #define SPI_I2SCTL_I2SEN_Pos (0) |
SPI_T::I2SCTL: I2SEN Position
| #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) |
SPI_T::I2SCTL: LZCEN Mask
| #define SPI_I2SCTL_LZCEN_Pos (17) |
SPI_T::I2SCTL: LZCEN Position
| #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) |
SPI_T::I2SCTL: LZCIEN Mask
| #define SPI_I2SCTL_LZCIEN_Pos (25) |
SPI_T::I2SCTL: LZCIEN Position
| #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) |
SPI_T::I2SCTL: MCLKEN Mask
| #define SPI_I2SCTL_MCLKEN_Pos (15) |
SPI_T::I2SCTL: MCLKEN Position
| #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) |
SPI_T::I2SCTL: MONO Mask
| #define SPI_I2SCTL_MONO_Pos (6) |
SPI_T::I2SCTL: MONO Position
| #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) |
SPI_T::I2SCTL: MUTE Mask
| #define SPI_I2SCTL_MUTE_Pos (3) |
SPI_T::I2SCTL: MUTE Position
| #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) |
SPI_T::I2SCTL: ORDER Mask
| #define SPI_I2SCTL_ORDER_Pos (7) |
SPI_T::I2SCTL: ORDER Position
| #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) |
SPI_T::I2SCTL: RXEN Mask
| #define SPI_I2SCTL_RXEN_Pos (2) |
SPI_T::I2SCTL: RXEN Position
| #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) |
SPI_T::I2SCTL: RXLCH Mask
| #define SPI_I2SCTL_RXLCH_Pos (23) |
SPI_T::I2SCTL: RXLCH Position
| #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) |
SPI_T::I2SCTL: RZCEN Mask
| #define SPI_I2SCTL_RZCEN_Pos (16) |
SPI_T::I2SCTL: RZCEN Position
| #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) |
SPI_T::I2SCTL: RZCIEN Mask
| #define SPI_I2SCTL_RZCIEN_Pos (24) |
SPI_T::I2SCTL: RZCIEN Position
| #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) |
SPI_T::I2SCTL: SLAVE Mask
| #define SPI_I2SCTL_SLAVE_Pos (8) |
SPI_T::I2SCTL: SLAVE Position
| #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) |
SPI_T::I2SCTL: TXEN Mask
| #define SPI_I2SCTL_TXEN_Pos (1) |
SPI_T::I2SCTL: TXEN Position
| #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) |
SPI_T::I2SCTL: WDWIDTH Mask
| #define SPI_I2SCTL_WDWIDTH_Pos (4) |
SPI_T::I2SCTL: WDWIDTH Position
| #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) |
SPI_T::I2SSTS: I2SENSTS Mask
| #define SPI_I2SSTS_I2SENSTS_Pos (15) |
SPI_T::I2SSTS: I2SENSTS Position
| #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) |
SPI_T::I2SSTS: LZCIF Mask
| #define SPI_I2SSTS_LZCIF_Pos (21) |
SPI_T::I2SSTS: LZCIF Position
| #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) |
SPI_T::I2SSTS: RIGHT Mask
| #define SPI_I2SSTS_RIGHT_Pos (4) |
SPI_T::I2SSTS: RIGHT Position
| #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) |
SPI_T::I2SSTS: RXCNT Mask
| #define SPI_I2SSTS_RXCNT_Pos (24) |
SPI_T::I2SSTS: RXCNT Position
| #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) |
SPI_T::I2SSTS: RXEMPTY Mask
| #define SPI_I2SSTS_RXEMPTY_Pos (8) |
SPI_T::I2SSTS: RXEMPTY Position
| #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) |
SPI_T::I2SSTS: RXFULL Mask
| #define SPI_I2SSTS_RXFULL_Pos (9) |
SPI_T::I2SSTS: RXFULL Position
| #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) |
SPI_T::I2SSTS: RXOVIF Mask
| #define SPI_I2SSTS_RXOVIF_Pos (11) |
SPI_T::I2SSTS: RXOVIF Position
| #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) |
SPI_T::I2SSTS: RXTHIF Mask
| #define SPI_I2SSTS_RXTHIF_Pos (10) |
SPI_T::I2SSTS: RXTHIF Position
| #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) |
SPI_T::I2SSTS: RXTOIF Mask
| #define SPI_I2SSTS_RXTOIF_Pos (12) |
SPI_T::I2SSTS: RXTOIF Position
| #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) |
SPI_T::I2SSTS: RZCIF Mask
| #define SPI_I2SSTS_RZCIF_Pos (20) |
SPI_T::I2SSTS: RZCIF Position
| #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) |
SPI_T::I2SSTS: TXCNT Mask
| #define SPI_I2SSTS_TXCNT_Pos (28) |
SPI_T::I2SSTS: TXCNT Position
| #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) |
SPI_T::I2SSTS: TXEMPTY Mask
| #define SPI_I2SSTS_TXEMPTY_Pos (16) |
SPI_T::I2SSTS: TXEMPTY Position
| #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) |
SPI_T::I2SSTS: TXFULL Mask
| #define SPI_I2SSTS_TXFULL_Pos (17) |
SPI_T::I2SSTS: TXFULL Position
| #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) |
SPI_T::I2SSTS: TXRXRST Mask
| #define SPI_I2SSTS_TXRXRST_Pos (23) |
SPI_T::I2SSTS: TXRXRST Position
| #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) |
SPI_T::I2SSTS: TXTHIF Mask
| #define SPI_I2SSTS_TXTHIF_Pos (18) |
SPI_T::I2SSTS: TXTHIF Position
| #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) |
SPI_T::I2SSTS: TXUFIF Mask
| #define SPI_I2SSTS_TXUFIF_Pos (19) |
SPI_T::I2SSTS: TXUFIF Position
| #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
SPI_T::PDMACTL: PDMARST Mask
| #define SPI_PDMACTL_PDMARST_Pos (2) |
SPI_T::PDMACTL: PDMARST Position
| #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
SPI_T::PDMACTL: RXPDMAEN Mask
| #define SPI_PDMACTL_RXPDMAEN_Pos (1) |
SPI_T::PDMACTL: RXPDMAEN Position
| #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
SPI_T::PDMACTL: TXPDMAEN Mask
| #define SPI_PDMACTL_TXPDMAEN_Pos (0) |
SPI_T::PDMACTL: TXPDMAEN Position
| #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) |
| #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
SPI_T::SSCTL: AUTOSS Mask
| #define SPI_SSCTL_AUTOSS_Pos (3) |
SPI_T::SSCTL: AUTOSS Position
| #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) |
SPI_T::SSCTL: SLV3WIRE Mask
| #define SPI_SSCTL_SLV3WIRE_Pos (4) |
SPI_T::SSCTL: SLV3WIRE Position
| #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) |
SPI_T::SSCTL: SLVBEIEN Mask
| #define SPI_SSCTL_SLVBEIEN_Pos (8) |
SPI_T::SSCTL: SLVBEIEN Position
| #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) |
SPI_T::SSCTL: SLVTOCNT Mask
| #define SPI_SSCTL_SLVTOCNT_Pos (16) |
SPI_T::SSCTL: SLVTOCNT Position
| #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) |
SPI_T::SSCTL: SLVTOIEN Mask
| #define SPI_SSCTL_SLVTOIEN_Pos (5) |
SPI_T::SSCTL: SLVTOIEN Position
| #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) |
SPI_T::SSCTL: SLVTORST Mask
| #define SPI_SSCTL_SLVTORST_Pos (6) |
SPI_T::SSCTL: SLVTORST Position
| #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) |
SPI_T::SSCTL: SLVURIEN Mask
| #define SPI_SSCTL_SLVURIEN_Pos (9) |
SPI_T::SSCTL: SLVURIEN Position
| #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) |
SPI_T::SSCTL: SS Mask
| #define SPI_SSCTL_SS_Pos (0) |
SPI_T::SSCTL: SS Position
| #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) |
SPI_T::SSCTL: SSACTIEN Mask
| #define SPI_SSCTL_SSACTIEN_Pos (12) |
SPI_T::SSCTL: SSACTIEN Position
| #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
SPI_T::SSCTL: SSACTPOL Mask
| #define SPI_SSCTL_SSACTPOL_Pos (2) |
SPI_T::SSCTL: SSACTPOL Position
| #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
SPI_T::SSCTL: SSINAIEN Mask
| #define SPI_SSCTL_SSINAIEN_Pos (13) |
SPI_T::SSCTL: SSINAIEN Position
| #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) |
SPI_T::STATUS: BUSY Mask
| #define SPI_STATUS_BUSY_Pos (0) |
SPI_T::STATUS: BUSY Position
| #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
SPI_T::STATUS: RXCNT Mask
| #define SPI_STATUS_RXCNT_Pos (24) |
SPI_T::STATUS: RXCNT Position
| #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
SPI_T::STATUS: RXEMPTY Mask
| #define SPI_STATUS_RXEMPTY_Pos (8) |
SPI_T::STATUS: RXEMPTY Position
| #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
SPI_T::STATUS: RXFULL Mask
| #define SPI_STATUS_RXFULL_Pos (9) |
SPI_T::STATUS: RXFULL Position
| #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
SPI_T::STATUS: RXOVIF Mask
| #define SPI_STATUS_RXOVIF_Pos (11) |
SPI_T::STATUS: RXOVIF Position
| #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
SPI_T::STATUS: RXTHIF Mask
| #define SPI_STATUS_RXTHIF_Pos (10) |
SPI_T::STATUS: RXTHIF Position
| #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
SPI_T::STATUS: RXTOIF Mask
| #define SPI_STATUS_RXTOIF_Pos (12) |
SPI_T::STATUS: RXTOIF Position
| #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) |
SPI_T::STATUS: SLVBEIF Mask
| #define SPI_STATUS_SLVBEIF_Pos (6) |
SPI_T::STATUS: SLVBEIF Position
| #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) |
SPI_T::STATUS: SLVTOIF Mask
| #define SPI_STATUS_SLVTOIF_Pos (5) |
SPI_T::STATUS: SLVTOIF Position
| #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) |
SPI_T::STATUS: SLVURIF Mask
| #define SPI_STATUS_SLVURIF_Pos (7) |
SPI_T::STATUS: SLVURIF Position
| #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) |
SPI_T::STATUS: SPIENSTS Mask
| #define SPI_STATUS_SPIENSTS_Pos (15) |
SPI_T::STATUS: SPIENSTS Position
| #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) |
SPI_T::STATUS: SSACTIF Mask
| #define SPI_STATUS_SSACTIF_Pos (2) |
SPI_T::STATUS: SSACTIF Position
| #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) |
SPI_T::STATUS: SSINAIF Mask
| #define SPI_STATUS_SSINAIF_Pos (3) |
SPI_T::STATUS: SSINAIF Position
| #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) |
SPI_T::STATUS: SSLINE Mask
| #define SPI_STATUS_SSLINE_Pos (4) |
SPI_T::STATUS: SSLINE Position
| #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
SPI_T::STATUS: TXCNT Mask
| #define SPI_STATUS_TXCNT_Pos (28) |
SPI_T::STATUS: TXCNT Position
| #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
SPI_T::STATUS: TXEMPTY Mask
| #define SPI_STATUS_TXEMPTY_Pos (16) |
SPI_T::STATUS: TXEMPTY Position
| #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
SPI_T::STATUS: TXFULL Mask
| #define SPI_STATUS_TXFULL_Pos (17) |
SPI_T::STATUS: TXFULL Position
| #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) |
SPI_T::STATUS: TXRXRST Mask
| #define SPI_STATUS_TXRXRST_Pos (23) |
SPI_T::STATUS: TXRXRST Position
| #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
SPI_T::STATUS: TXTHIF Mask
| #define SPI_STATUS_TXTHIF_Pos (18) |
SPI_T::STATUS: TXTHIF Position
| #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) |
SPI_T::STATUS: TXUFIF Mask
| #define SPI_STATUS_TXUFIF_Pos (19) |
SPI_T::STATUS: TXUFIF Position
| #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
SPI_T::STATUS: UNITIF Mask
| #define SPI_STATUS_UNITIF_Pos (1) |
SPI_T::STATUS: UNITIF Position
| #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) |
| #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
SYS_T::BODCTL: BODDGSEL Mask
| #define SYS_BODCTL_BODDGSEL_Pos (8) |
SYS_T::BODCTL: BODDGSEL Position
| #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
SYS_T::BODCTL: BODEN Mask
| #define SYS_BODCTL_BODEN_Pos (0) |
SYS_T::BODCTL: BODEN Position
| #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
SYS_T::BODCTL: BODIF Mask
| #define SYS_BODCTL_BODIF_Pos (4) |
SYS_T::BODCTL: BODIF Position
| #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) |
SYS_T::BODCTL: BODLPM Mask
| #define SYS_BODCTL_BODLPM_Pos (5) |
SYS_T::BODCTL: BODLPM Position
| #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
SYS_T::BODCTL: BODOUT Mask
| #define SYS_BODCTL_BODOUT_Pos (6) |
SYS_T::BODCTL: BODOUT Position
| #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) |
SYS_T::BODCTL: BODRSTEN Mask
| #define SYS_BODCTL_BODRSTEN_Pos (3) |
SYS_T::BODCTL: BODRSTEN Position
| #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) |
SYS_T::BODCTL: BODVL Mask
| #define SYS_BODCTL_BODVL_Pos (1) |
SYS_T::BODCTL: BODVL Position
| #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
SYS_T::BODCTL: LVRDGSEL Mask
| #define SYS_BODCTL_LVRDGSEL_Pos (12) |
SYS_T::BODCTL: LVRDGSEL Position
| #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
SYS_T::BODCTL: LVREN Mask
| #define SYS_BODCTL_LVREN_Pos (7) |
SYS_T::BODCTL: LVREN Position
| #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
SYS_T::GPA_MFPH: PA10MFP Mask
| #define SYS_GPA_MFPH_PA10MFP_Pos (8) |
SYS_T::GPA_MFPH: PA10MFP Position
| #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
SYS_T::GPA_MFPH: PA11MFP Mask
| #define SYS_GPA_MFPH_PA11MFP_Pos (12) |
SYS_T::GPA_MFPH: PA11MFP Position
| #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
SYS_T::GPA_MFPH: PA12MFP Mask
| #define SYS_GPA_MFPH_PA12MFP_Pos (16) |
SYS_T::GPA_MFPH: PA12MFP Position
| #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
SYS_T::GPA_MFPH: PA13MFP Mask
| #define SYS_GPA_MFPH_PA13MFP_Pos (20) |
SYS_T::GPA_MFPH: PA13MFP Position
| #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
SYS_T::GPA_MFPH: PA14MFP Mask
| #define SYS_GPA_MFPH_PA14MFP_Pos (24) |
SYS_T::GPA_MFPH: PA14MFP Position
| #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
SYS_T::GPA_MFPH: PA15MFP Mask
| #define SYS_GPA_MFPH_PA15MFP_Pos (28) |
SYS_T::GPA_MFPH: PA15MFP Position
| #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
SYS_T::GPA_MFPH: PA8MFP Mask
| #define SYS_GPA_MFPH_PA8MFP_Pos (0) |
SYS_T::GPA_MFPH: PA8MFP Position
| #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
SYS_T::GPA_MFPH: PA9MFP Mask
| #define SYS_GPA_MFPH_PA9MFP_Pos (4) |
SYS_T::GPA_MFPH: PA9MFP Position
| #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
SYS_T::GPA_MFPL: PA0MFP Mask
| #define SYS_GPA_MFPL_PA0MFP_Pos (0) |
SYS_T::GPA_MFPL: PA0MFP Position
| #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
SYS_T::GPA_MFPL: PA1MFP Mask
| #define SYS_GPA_MFPL_PA1MFP_Pos (4) |
SYS_T::GPA_MFPL: PA1MFP Position
| #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
SYS_T::GPA_MFPL: PA2MFP Mask
| #define SYS_GPA_MFPL_PA2MFP_Pos (8) |
SYS_T::GPA_MFPL: PA2MFP Position
| #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
SYS_T::GPA_MFPL: PA3MFP Mask
| #define SYS_GPA_MFPL_PA3MFP_Pos (12) |
SYS_T::GPA_MFPL: PA3MFP Position
| #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
SYS_T::GPA_MFPL: PA4MFP Mask
| #define SYS_GPA_MFPL_PA4MFP_Pos (16) |
SYS_T::GPA_MFPL: PA4MFP Position
| #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
SYS_T::GPA_MFPL: PA5MFP Mask
| #define SYS_GPA_MFPL_PA5MFP_Pos (20) |
SYS_T::GPA_MFPL: PA5MFP Position
| #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
SYS_T::GPA_MFPL: PA6MFP Mask
| #define SYS_GPA_MFPL_PA6MFP_Pos (24) |
SYS_T::GPA_MFPL: PA6MFP Position
| #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) |
SYS_T::GPA_MFPL: PA7MFP Mask
| #define SYS_GPA_MFPL_PA7MFP_Pos (28) |
SYS_T::GPA_MFPL: PA7MFP Position
| #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
SYS_T::GPB_MFPH: PB10MFP Mask
| #define SYS_GPB_MFPH_PB10MFP_Pos (8) |
SYS_T::GPB_MFPH: PB10MFP Position
| #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
SYS_T::GPB_MFPH: PB11MFP Mask
| #define SYS_GPB_MFPH_PB11MFP_Pos (12) |
SYS_T::GPB_MFPH: PB11MFP Position
| #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) |
SYS_T::GPB_MFPH: PB12MFP Mask
| #define SYS_GPB_MFPH_PB12MFP_Pos (16) |
SYS_T::GPB_MFPH: PB12MFP Position
| #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
SYS_T::GPB_MFPH: PB13MFP Mask
| #define SYS_GPB_MFPH_PB13MFP_Pos (20) |
SYS_T::GPB_MFPH: PB13MFP Position
| #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
SYS_T::GPB_MFPH: PB14MFP Mask
| #define SYS_GPB_MFPH_PB14MFP_Pos (24) |
SYS_T::GPB_MFPH: PB14MFP Position
| #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
SYS_T::GPB_MFPH: PB15MFP Mask
| #define SYS_GPB_MFPH_PB15MFP_Pos (28) |
SYS_T::GPB_MFPH: PB15MFP Position
| #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
SYS_T::GPB_MFPH: PB8MFP Mask
| #define SYS_GPB_MFPH_PB8MFP_Pos (0) |
SYS_T::GPB_MFPH: PB8MFP Position
| #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
SYS_T::GPB_MFPH: PB9MFP Mask
| #define SYS_GPB_MFPH_PB9MFP_Pos (4) |
SYS_T::GPB_MFPH: PB9MFP Position
| #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
SYS_T::GPB_MFPL: PB0MFP Mask
| #define SYS_GPB_MFPL_PB0MFP_Pos (0) |
SYS_T::GPB_MFPL: PB0MFP Position
| #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
SYS_T::GPB_MFPL: PB1MFP Mask
| #define SYS_GPB_MFPL_PB1MFP_Pos (4) |
SYS_T::GPB_MFPL: PB1MFP Position
| #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
SYS_T::GPB_MFPL: PB2MFP Mask
| #define SYS_GPB_MFPL_PB2MFP_Pos (8) |
SYS_T::GPB_MFPL: PB2MFP Position
| #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
SYS_T::GPB_MFPL: PB3MFP Mask
| #define SYS_GPB_MFPL_PB3MFP_Pos (12) |
SYS_T::GPB_MFPL: PB3MFP Position
| #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
SYS_T::GPB_MFPL: PB4MFP Mask
| #define SYS_GPB_MFPL_PB4MFP_Pos (16) |
SYS_T::GPB_MFPL: PB4MFP Position
| #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
SYS_T::GPB_MFPL: PB5MFP Mask
| #define SYS_GPB_MFPL_PB5MFP_Pos (20) |
SYS_T::GPB_MFPL: PB5MFP Position
| #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
SYS_T::GPB_MFPL: PB6MFP Mask
| #define SYS_GPB_MFPL_PB6MFP_Pos (24) |
SYS_T::GPB_MFPL: PB6MFP Position
| #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
SYS_T::GPB_MFPL: PB7MFP Mask
| #define SYS_GPB_MFPL_PB7MFP_Pos (28) |
SYS_T::GPB_MFPL: PB7MFP Position
| #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
SYS_T::GPC_MFPH: PC10MFP Mask
| #define SYS_GPC_MFPH_PC10MFP_Pos (8) |
SYS_T::GPC_MFPH: PC10MFP Position
| #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
SYS_T::GPC_MFPH: PC11MFP Mask
| #define SYS_GPC_MFPH_PC11MFP_Pos (12) |
SYS_T::GPC_MFPH: PC11MFP Position
| #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) |
SYS_T::GPC_MFPH: PC12MFP Mask
| #define SYS_GPC_MFPH_PC12MFP_Pos (16) |
SYS_T::GPC_MFPH: PC12MFP Position
| #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) |
SYS_T::GPC_MFPH: PC13MFP Mask
| #define SYS_GPC_MFPH_PC13MFP_Pos (20) |
SYS_T::GPC_MFPH: PC13MFP Position
| #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
SYS_T::GPC_MFPH: PC14MFP Mask
| #define SYS_GPC_MFPH_PC14MFP_Pos (24) |
SYS_T::GPC_MFPH: PC14MFP Position
| #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
SYS_T::GPC_MFPH: PC15MFP Mask
| #define SYS_GPC_MFPH_PC15MFP_Pos (28) |
SYS_T::GPC_MFPH: PC15MFP Position
| #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
SYS_T::GPC_MFPH: PC8MFP Mask
| #define SYS_GPC_MFPH_PC8MFP_Pos (0) |
SYS_T::GPC_MFPH: PC8MFP Position
| #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
SYS_T::GPC_MFPH: PC9MFP Mask
| #define SYS_GPC_MFPH_PC9MFP_Pos (4) |
SYS_T::GPC_MFPH: PC9MFP Position
| #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
SYS_T::GPC_MFPL: PC0MFP Mask
| #define SYS_GPC_MFPL_PC0MFP_Pos (0) |
SYS_T::GPC_MFPL: PC0MFP Position
| #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
SYS_T::GPC_MFPL: PC1MFP Mask
| #define SYS_GPC_MFPL_PC1MFP_Pos (4) |
SYS_T::GPC_MFPL: PC1MFP Position
| #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
SYS_T::GPC_MFPL: PC2MFP Mask
| #define SYS_GPC_MFPL_PC2MFP_Pos (8) |
SYS_T::GPC_MFPL: PC2MFP Position
| #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
SYS_T::GPC_MFPL: PC3MFP Mask
| #define SYS_GPC_MFPL_PC3MFP_Pos (12) |
SYS_T::GPC_MFPL: PC3MFP Position
| #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) |
SYS_T::GPC_MFPL: PC4MFP Mask
| #define SYS_GPC_MFPL_PC4MFP_Pos (16) |
SYS_T::GPC_MFPL: PC4MFP Position
| #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) |
SYS_T::GPC_MFPL: PC5MFP Mask
| #define SYS_GPC_MFPL_PC5MFP_Pos (20) |
SYS_T::GPC_MFPL: PC5MFP Position
| #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
SYS_T::GPC_MFPL: PC6MFP Mask
| #define SYS_GPC_MFPL_PC6MFP_Pos (24) |
SYS_T::GPC_MFPL: PC6MFP Position
| #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
SYS_T::GPC_MFPL: PC7MFP Mask
| #define SYS_GPC_MFPL_PC7MFP_Pos (28) |
SYS_T::GPC_MFPL: PC7MFP Position
| #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) |
SYS_T::GPD_MFPH: PD10MFP Mask
| #define SYS_GPD_MFPH_PD10MFP_Pos (8) |
SYS_T::GPD_MFPH: PD10MFP Position
| #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) |
SYS_T::GPD_MFPH: PD11MFP Mask
| #define SYS_GPD_MFPH_PD11MFP_Pos (12) |
SYS_T::GPD_MFPH: PD11MFP Position
| #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) |
SYS_T::GPD_MFPH: PD12MFP Mask
| #define SYS_GPD_MFPH_PD12MFP_Pos (16) |
SYS_T::GPD_MFPH: PD12MFP Position
| #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) |
SYS_T::GPD_MFPH: PD13MFP Mask
| #define SYS_GPD_MFPH_PD13MFP_Pos (20) |
SYS_T::GPD_MFPH: PD13MFP Position
| #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
SYS_T::GPD_MFPH: PD14MFP Mask
| #define SYS_GPD_MFPH_PD14MFP_Pos (24) |
SYS_T::GPD_MFPH: PD14MFP Position
| #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) |
SYS_T::GPD_MFPH: PD15MFP Mask
| #define SYS_GPD_MFPH_PD15MFP_Pos (28) |
SYS_T::GPD_MFPH: PD15MFP Position
| #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) |
SYS_T::GPD_MFPH: PD8MFP Mask
| #define SYS_GPD_MFPH_PD8MFP_Pos (0) |
SYS_T::GPD_MFPH: PD8MFP Position
| #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) |
SYS_T::GPD_MFPH: PD9MFP Mask
| #define SYS_GPD_MFPH_PD9MFP_Pos (4) |
SYS_T::GPD_MFPH: PD9MFP Position
| #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) |
SYS_T::GPD_MFPL: PD0MFP Mask
| #define SYS_GPD_MFPL_PD0MFP_Pos (0) |
SYS_T::GPD_MFPL: PD0MFP Position
| #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) |
SYS_T::GPD_MFPL: PD1MFP Mask
| #define SYS_GPD_MFPL_PD1MFP_Pos (4) |
SYS_T::GPD_MFPL: PD1MFP Position
| #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) |
SYS_T::GPD_MFPL: PD2MFP Mask
| #define SYS_GPD_MFPL_PD2MFP_Pos (8) |
SYS_T::GPD_MFPL: PD2MFP Position
| #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) |
SYS_T::GPD_MFPL: PD3MFP Mask
| #define SYS_GPD_MFPL_PD3MFP_Pos (12) |
SYS_T::GPD_MFPL: PD3MFP Position
| #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) |
SYS_T::GPD_MFPL: PD4MFP Mask
| #define SYS_GPD_MFPL_PD4MFP_Pos (16) |
SYS_T::GPD_MFPL: PD4MFP Position
| #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) |
SYS_T::GPD_MFPL: PD5MFP Mask
| #define SYS_GPD_MFPL_PD5MFP_Pos (20) |
SYS_T::GPD_MFPL: PD5MFP Position
| #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
SYS_T::GPD_MFPL: PD6MFP Mask
| #define SYS_GPD_MFPL_PD6MFP_Pos (24) |
SYS_T::GPD_MFPL: PD6MFP Position
| #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
SYS_T::GPD_MFPL: PD7MFP Mask
| #define SYS_GPD_MFPL_PD7MFP_Pos (28) |
SYS_T::GPD_MFPL: PD7MFP Position
| #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) |
SYS_T::GPE_MFPH: PE10MFP Mask
| #define SYS_GPE_MFPH_PE10MFP_Pos (8) |
SYS_T::GPE_MFPH: PE10MFP Position
| #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) |
SYS_T::GPE_MFPH: PE11MFP Mask
| #define SYS_GPE_MFPH_PE11MFP_Pos (12) |
SYS_T::GPE_MFPH: PE11MFP Position
| #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) |
SYS_T::GPE_MFPH: PE12MFP Mask
| #define SYS_GPE_MFPH_PE12MFP_Pos (16) |
SYS_T::GPE_MFPH: PE12MFP Position
| #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) |
SYS_T::GPE_MFPH: PE13MFP Mask
| #define SYS_GPE_MFPH_PE13MFP_Pos (20) |
SYS_T::GPE_MFPH: PE13MFP Position
| #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) |
SYS_T::GPE_MFPH: PE14MFP Mask
| #define SYS_GPE_MFPH_PE14MFP_Pos (24) |
SYS_T::GPE_MFPH: PE14MFP Position
| #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) |
SYS_T::GPE_MFPH: PE8MFP Mask
| #define SYS_GPE_MFPH_PE8MFP_Pos (0) |
SYS_T::GPE_MFPH: PE8MFP Position
| #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) |
SYS_T::GPE_MFPH: PE9MFP Mask
| #define SYS_GPE_MFPH_PE9MFP_Pos (4) |
SYS_T::GPE_MFPH: PE9MFP Position
| #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) |
SYS_T::GPE_MFPL: PE0MFP Mask
| #define SYS_GPE_MFPL_PE0MFP_Pos (0) |
SYS_T::GPE_MFPL: PE0MFP Position
| #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) |
SYS_T::GPE_MFPL: PE1MFP Mask
| #define SYS_GPE_MFPL_PE1MFP_Pos (4) |
SYS_T::GPE_MFPL: PE1MFP Position
| #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) |
SYS_T::GPE_MFPL: PE2MFP Mask
| #define SYS_GPE_MFPL_PE2MFP_Pos (8) |
SYS_T::GPE_MFPL: PE2MFP Position
| #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) |
SYS_T::GPE_MFPL: PE3MFP Mask
| #define SYS_GPE_MFPL_PE3MFP_Pos (12) |
SYS_T::GPE_MFPL: PE3MFP Position
| #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) |
SYS_T::GPE_MFPL: PE4MFP Mask
| #define SYS_GPE_MFPL_PE4MFP_Pos (16) |
SYS_T::GPE_MFPL: PE4MFP Position
| #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
SYS_T::GPE_MFPL: PE5MFP Mask
| #define SYS_GPE_MFPL_PE5MFP_Pos (20) |
SYS_T::GPE_MFPL: PE5MFP Position
| #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) |
SYS_T::GPE_MFPL: PE6MFP Mask
| #define SYS_GPE_MFPL_PE6MFP_Pos (24) |
SYS_T::GPE_MFPL: PE6MFP Position
| #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) |
SYS_T::GPE_MFPL: PE7MFP Mask
| #define SYS_GPE_MFPL_PE7MFP_Pos (28) |
SYS_T::GPE_MFPL: PE7MFP Position
| #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
SYS_T::GPF_MFPL: PF0MFP Mask
| #define SYS_GPF_MFPL_PF0MFP_Pos (0) |
SYS_T::GPF_MFPL: PF0MFP Position
| #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
SYS_T::GPF_MFPL: PF1MFP Mask
| #define SYS_GPF_MFPL_PF1MFP_Pos (4) |
SYS_T::GPF_MFPL: PF1MFP Position
| #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
SYS_T::GPF_MFPL: PF2MFP Mask
| #define SYS_GPF_MFPL_PF2MFP_Pos (8) |
SYS_T::GPF_MFPL: PF2MFP Position
| #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
SYS_T::GPF_MFPL: PF3MFP Mask
| #define SYS_GPF_MFPL_PF3MFP_Pos (12) |
SYS_T::GPF_MFPL: PF3MFP Position
| #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) |
SYS_T::GPF_MFPL: PF4MFP Mask
| #define SYS_GPF_MFPL_PF4MFP_Pos (16) |
SYS_T::GPF_MFPL: PF4MFP Position
| #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) |
SYS_T::GPF_MFPL: PF5MFP Mask
| #define SYS_GPF_MFPL_PF5MFP_Pos (20) |
SYS_T::GPF_MFPL: PF5MFP Position
| #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
SYS_T::GPF_MFPL: PF6MFP Mask
| #define SYS_GPF_MFPL_PF6MFP_Pos (24) |
SYS_T::GPF_MFPL: PF6MFP Position
| #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
SYS_T::GPF_MFPL: PF7MFP Mask
| #define SYS_GPF_MFPL_PF7MFP_Pos (28) |
SYS_T::GPF_MFPL: PF7MFP Position
| #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) |
SYS_T::IPRST0: CHIPRST Mask
| #define SYS_IPRST0_CHIPRST_Pos (0) |
SYS_T::IPRST0: CHIPRST Position
| #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) |
SYS_T::IPRST0: CPURST Mask
| #define SYS_IPRST0_CPURST_Pos (1) |
SYS_T::IPRST0: CPURST Position
| #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) |
SYS_T::IPRST0: CRCRST Mask
| #define SYS_IPRST0_CRCRST_Pos (7) |
SYS_T::IPRST0: CRCRST Position
| #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) |
SYS_T::IPRST0: EBIRST Mask
| #define SYS_IPRST0_EBIRST_Pos (3) |
SYS_T::IPRST0: EBIRST Position
| #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) |
SYS_T::IPRST0: PDMARST Mask
| #define SYS_IPRST0_PDMARST_Pos (2) |
SYS_T::IPRST0: PDMARST Position
| #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) |
SYS_T::IPRST0: USBHRST Mask
| #define SYS_IPRST0_USBHRST_Pos (4) |
SYS_T::IPRST0: USBHRST Position
| #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) |
SYS_T::IPRST1: EADCRST Mask
| #define SYS_IPRST1_EADCRST_Pos (28) |
SYS_T::IPRST1: EADCRST Position
| #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) |
SYS_T::IPRST1: GPIORST Mask
| #define SYS_IPRST1_GPIORST_Pos (1) |
SYS_T::IPRST1: GPIORST Position
| #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) |
SYS_T::IPRST1: I2C0RST Mask
| #define SYS_IPRST1_I2C0RST_Pos (8) |
SYS_T::IPRST1: I2C0RST Position
| #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) |
SYS_T::IPRST1: I2C1RST Mask
| #define SYS_IPRST1_I2C1RST_Pos (9) |
SYS_T::IPRST1: I2C1RST Position
| #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) |
SYS_T::IPRST1: SPI0RST Mask
| #define SYS_IPRST1_SPI0RST_Pos (12) |
SYS_T::IPRST1: SPI0RST Position
| #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) |
SYS_T::IPRST1: SPI1RST Mask
| #define SYS_IPRST1_SPI1RST_Pos (13) |
SYS_T::IPRST1: SPI1RST Position
| #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) |
SYS_T::IPRST1: TMR0RST Mask
| #define SYS_IPRST1_TMR0RST_Pos (2) |
SYS_T::IPRST1: TMR0RST Position
| #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) |
SYS_T::IPRST1: TMR1RST Mask
| #define SYS_IPRST1_TMR1RST_Pos (3) |
SYS_T::IPRST1: TMR1RST Position
| #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) |
SYS_T::IPRST1: TMR2RST Mask
| #define SYS_IPRST1_TMR2RST_Pos (4) |
SYS_T::IPRST1: TMR2RST Position
| #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) |
SYS_T::IPRST1: TMR3RST Mask
| #define SYS_IPRST1_TMR3RST_Pos (5) |
SYS_T::IPRST1: TMR3RST Position
| #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) |
SYS_T::IPRST1: UART0RST Mask
| #define SYS_IPRST1_UART0RST_Pos (16) |
SYS_T::IPRST1: UART0RST Position
| #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) |
SYS_T::IPRST1: UART1RST Mask
| #define SYS_IPRST1_UART1RST_Pos (17) |
SYS_T::IPRST1: UART1RST Position
| #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) |
SYS_T::IPRST1: UART2RST Mask
| #define SYS_IPRST1_UART2RST_Pos (18) |
SYS_T::IPRST1: UART2RST Position
| #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) |
SYS_T::IPRST1: UART3RST Mask
| #define SYS_IPRST1_UART3RST_Pos (19) |
SYS_T::IPRST1: UART3RST Position
| #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) |
SYS_T::IPRST1: USBDRST Mask
| #define SYS_IPRST1_USBDRST_Pos (27) |
SYS_T::IPRST1: USBDRST Position
| #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
SYS_T::IPRST2: PWM0RST Mask
| #define SYS_IPRST2_PWM0RST_Pos (16) |
SYS_T::IPRST2: PWM0RST Position
| #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) |
SYS_T::IPRST2: PWM1RST Mask
| #define SYS_IPRST2_PWM1RST_Pos (17) |
SYS_T::IPRST2: PWM1RST Position
| #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
SYS_T::IPRST2: SC0RST Mask
| #define SYS_IPRST2_SC0RST_Pos (0) |
SYS_T::IPRST2: SC0RST Position
| #define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) |
SYS_T::IPRST2: TKRST Mask
| #define SYS_IPRST2_TKRST_Pos (25) |
SYS_T::IPRST2: TKRST Position
| #define SYS_IRC48MTCTL_CESTOPEN_Msk (0x1ul << SYS_IRC48MTCTL_CESTOPEN_Pos) |
SYS_T::IRC48MTCTL: CESTOPEN Mask
| #define SYS_IRC48MTCTL_CESTOPEN_Pos (8) |
SYS_T::IRC48MTCTL: CESTOPEN Position
| #define SYS_IRC48MTCTL_FREQSEL_Msk (0x3ul << SYS_IRC48MTCTL_FREQSEL_Pos) |
SYS_T::IRC48MTCTL: FREQSEL Mask
| #define SYS_IRC48MTCTL_FREQSEL_Pos (0) |
SYS_T::IRC48MTCTL: FREQSEL Position
| #define SYS_IRC48MTCTL_LOOPSEL_Msk (0x3ul << SYS_IRC48MTCTL_LOOPSEL_Pos) |
SYS_T::IRC48MTCTL: LOOPSEL Mask
| #define SYS_IRC48MTCTL_LOOPSEL_Pos (4) |
SYS_T::IRC48MTCTL: LOOPSEL Position
| #define SYS_IRC48MTCTL_REFCKSEL_Msk (0x1ul << SYS_IRC48MTCTL_REFCKSEL_Pos) |
SYS_T::IRC48MTCTL: REFCKSEL Mask
| #define SYS_IRC48MTCTL_REFCKSEL_Pos (10) |
SYS_T::IRC48MTCTL: REFCKSEL Position
| #define SYS_IRC48MTCTL_RETRYCNT_Msk (0x3ul << SYS_IRC48MTCTL_RETRYCNT_Pos) |
SYS_T::IRC48MTCTL: RETRYCNT Mask
| #define SYS_IRC48MTCTL_RETRYCNT_Pos (6) |
SYS_T::IRC48MTCTL: RETRYCNT Position
| #define SYS_IRC48MTIEN_CLKEIEN_Msk (0x1ul << SYS_IRC48MTIEN_CLKEIEN_Pos) |
SYS_T::IRC48MTIEN: CLKEIEN Mask
| #define SYS_IRC48MTIEN_CLKEIEN_Pos (2) |
SYS_T::IRC48MTIEN: CLKEIEN Position
| #define SYS_IRC48MTIEN_TFAILIEN_Msk (0x1ul << SYS_IRC48MTIEN_TFAILIEN_Pos) |
SYS_T::IRC48MTIEN: TFAILIEN Mask
| #define SYS_IRC48MTIEN_TFAILIEN_Pos (1) |
SYS_T::IRC48MTIEN: TFAILIEN Position
| #define SYS_IRC48MTISTS_CLKERRIF_Msk (0x1ul << SYS_IRC48MTISTS_CLKERRIF_Pos) |
SYS_T::IRC48MTISTS: CLKERRIF Mask
| #define SYS_IRC48MTISTS_CLKERRIF_Pos (2) |
SYS_T::IRC48MTISTS: CLKERRIF Position
| #define SYS_IRC48MTISTS_FREQLOCK_Msk (0x1ul << SYS_IRC48MTISTS_FREQLOCK_Pos) |
SYS_T::IRC48MTISTS: FREQLOCK Mask
| #define SYS_IRC48MTISTS_FREQLOCK_Pos (0) |
SYS_T::IRC48MTISTS: FREQLOCK Position
| #define SYS_IRC48MTISTS_TFAILIF_Msk (0x1ul << SYS_IRC48MTISTS_TFAILIF_Pos) |
SYS_T::IRC48MTISTS: TFAILIF Mask
| #define SYS_IRC48MTISTS_TFAILIF_Pos (1) |
SYS_T::IRC48MTISTS: TFAILIF Position
| #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) |
SYS_T::IRCTCTL: CESTOPEN Mask
| #define SYS_IRCTCTL_CESTOPEN_Pos (8) |
SYS_T::IRCTCTL: CESTOPEN Position
| #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) |
SYS_T::IRCTCTL: FREQSEL Mask
| #define SYS_IRCTCTL_FREQSEL_Pos (0) |
SYS_T::IRCTCTL: FREQSEL Position
| #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) |
SYS_T::IRCTCTL: LOOPSEL Mask
| #define SYS_IRCTCTL_LOOPSEL_Pos (4) |
SYS_T::IRCTCTL: LOOPSEL Position
| #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) |
SYS_T::IRCTCTL: RETRYCNT Mask
| #define SYS_IRCTCTL_RETRYCNT_Pos (6) |
SYS_T::IRCTCTL: RETRYCNT Position
| #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) |
SYS_T::IRCTIEN: CLKEIEN Mask
| #define SYS_IRCTIEN_CLKEIEN_Pos (2) |
SYS_T::IRCTIEN: CLKEIEN Position
| #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) |
SYS_T::IRCTIEN: TFAILIEN Mask
| #define SYS_IRCTIEN_TFAILIEN_Pos (1) |
SYS_T::IRCTIEN: TFAILIEN Position
| #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) |
SYS_T::IRCTISTS: CLKERRIF Mask
| #define SYS_IRCTISTS_CLKERRIF_Pos (2) |
SYS_T::IRCTISTS: CLKERRIF Position
| #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) |
SYS_T::IRCTISTS: FREQLOCK Mask
| #define SYS_IRCTISTS_FREQLOCK_Pos (0) |
SYS_T::IRCTISTS: FREQLOCK Position
| #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) |
SYS_T::IRCTISTS: TFAILIF Mask
| #define SYS_IRCTISTS_TFAILIF_Pos (1) |
SYS_T::IRCTISTS: TFAILIF Position
| #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) |
SYS_T::IVSCTL: VBATUGEN Mask
| #define SYS_IVSCTL_VBATUGEN_Pos (1) |
SYS_T::IVSCTL: VBATUGEN Position
| #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) |
SYS_T::IVSCTL: VTEMPEN Mask
| #define SYS_IVSCTL_VTEMPEN_Pos (0) |
SYS_T::IVSCTL: VTEMPEN Position
| #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) |
SYS_INT_T::NMIEN: BODOUT Mask
| #define SYS_NMIEN_BODOUT_Pos (0) |
@addtogroup INT_CONST INT Bit Field Definition Constant Definitions for SYS Controller
SYS_INT_T::NMIEN: BODOUT Position
| #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) |
SYS_INT_T::NMIEN: CLKFAIL Mask
| #define SYS_NMIEN_CLKFAIL_Pos (4) |
SYS_INT_T::NMIEN: CLKFAIL Position
| #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) |
SYS_INT_T::NMIEN: EINT0 Mask
| #define SYS_NMIEN_EINT0_Pos (8) |
SYS_INT_T::NMIEN: EINT0 Position
| #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) |
SYS_INT_T::NMIEN: EINT1 Mask
| #define SYS_NMIEN_EINT1_Pos (9) |
SYS_INT_T::NMIEN: EINT1 Position
| #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) |
SYS_INT_T::NMIEN: EINT2 Mask
| #define SYS_NMIEN_EINT2_Pos (10) |
SYS_INT_T::NMIEN: EINT2 Position
| #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) |
SYS_INT_T::NMIEN: EINT3 Mask
| #define SYS_NMIEN_EINT3_Pos (11) |
SYS_INT_T::NMIEN: EINT3 Position
| #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) |
SYS_INT_T::NMIEN: EINT4 Mask
| #define SYS_NMIEN_EINT4_Pos (12) |
SYS_INT_T::NMIEN: EINT4 Position
| #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) |
SYS_INT_T::NMIEN: EINT5 Mask
| #define SYS_NMIEN_EINT5_Pos (13) |
SYS_INT_T::NMIEN: EINT5 Position
| #define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) |
SYS_INT_T::NMIEN: IRC_INT Mask
| #define SYS_NMIEN_IRC_INT_Pos (1) |
SYS_INT_T::NMIEN: IRC_INT Position
| #define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) |
SYS_INT_T::NMIEN: PWRWU_INT Mask
| #define SYS_NMIEN_PWRWU_INT_Pos (2) |
SYS_INT_T::NMIEN: PWRWU_INT Position
| #define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) |
SYS_INT_T::NMIEN: RTC_INT Mask
| #define SYS_NMIEN_RTC_INT_Pos (6) |
SYS_INT_T::NMIEN: RTC_INT Position
| #define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) |
SYS_INT_T::NMIEN: TAMPER_INT Mask
| #define SYS_NMIEN_TAMPER_INT_Pos (7) |
SYS_INT_T::NMIEN: TAMPER_INT Position
| #define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) |
SYS_INT_T::NMIEN: UART0_INT Mask
| #define SYS_NMIEN_UART0_INT_Pos (14) |
SYS_INT_T::NMIEN: UART0_INT Position
| #define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) |
SYS_INT_T::NMIEN: UART1_INT Mask
| #define SYS_NMIEN_UART1_INT_Pos (15) |
SYS_INT_T::NMIEN: UART1_INT Position
| #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) |
SYS_INT_T::NMISTS: BODOUT Mask
| #define SYS_NMISTS_BODOUT_Pos (0) |
SYS_INT_T::NMISTS: BODOUT Position
| #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) |
SYS_INT_T::NMISTS: CLKFAIL Mask
| #define SYS_NMISTS_CLKFAIL_Pos (4) |
SYS_INT_T::NMISTS: CLKFAIL Position
| #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) |
SYS_INT_T::NMISTS: EINT0 Mask
| #define SYS_NMISTS_EINT0_Pos (8) |
SYS_INT_T::NMISTS: EINT0 Position
| #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) |
SYS_INT_T::NMISTS: EINT1 Mask
| #define SYS_NMISTS_EINT1_Pos (9) |
SYS_INT_T::NMISTS: EINT1 Position
| #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) |
SYS_INT_T::NMISTS: EINT2 Mask
| #define SYS_NMISTS_EINT2_Pos (10) |
SYS_INT_T::NMISTS: EINT2 Position
| #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) |
SYS_INT_T::NMISTS: EINT3 Mask
| #define SYS_NMISTS_EINT3_Pos (11) |
SYS_INT_T::NMISTS: EINT3 Position
| #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) |
SYS_INT_T::NMISTS: EINT4 Mask
| #define SYS_NMISTS_EINT4_Pos (12) |
SYS_INT_T::NMISTS: EINT4 Position
| #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) |
SYS_INT_T::NMISTS: EINT5 Mask
| #define SYS_NMISTS_EINT5_Pos (13) |
SYS_INT_T::NMISTS: EINT5 Position
| #define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) |
SYS_INT_T::NMISTS: IRC_INT Mask
| #define SYS_NMISTS_IRC_INT_Pos (1) |
SYS_INT_T::NMISTS: IRC_INT Position
| #define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) |
SYS_INT_T::NMISTS: PWRWU_INT Mask
| #define SYS_NMISTS_PWRWU_INT_Pos (2) |
SYS_INT_T::NMISTS: PWRWU_INT Position
| #define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) |
SYS_INT_T::NMISTS: RTC_INT Mask
| #define SYS_NMISTS_RTC_INT_Pos (6) |
SYS_INT_T::NMISTS: RTC_INT Position
| #define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) |
SYS_INT_T::NMISTS: TAMPER_INT Mask
| #define SYS_NMISTS_TAMPER_INT_Pos (7) |
SYS_INT_T::NMISTS: TAMPER_INT Position
| #define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) |
SYS_INT_T::NMISTS: UART0_INT Mask
| #define SYS_NMISTS_UART0_INT_Pos (14) |
SYS_INT_T::NMISTS: UART0_INT Position
| #define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) |
SYS_INT_T::NMISTS: UART1_INT Mask
| #define SYS_NMISTS_UART1_INT_Pos (15) |
SYS_INT_T::NMISTS: UART1_INT Position
| #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
SYS_T::PDID: PDID Mask
| #define SYS_PDID_PDID_Pos (0) |
@addtogroup SYS_CONST SYS Bit Field Definition Constant Definitions for SYS Controller
SYS_T::PDID: PDID Position
| #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
SYS_T::PORCTL: POROFF Mask
| #define SYS_PORCTL_POROFF_Pos (0) |
SYS_T::PORCTL: POROFF Position
| #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) |
SYS_T::REGLCTL: REGLCTL Mask
| #define SYS_REGLCTL_REGLCTL_Pos (0) |
SYS_T::REGLCTL: REGLCTL Position
| #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
SYS_T::RSTSTS: BODRF Mask
| #define SYS_RSTSTS_BODRF_Pos (4) |
SYS_T::RSTSTS: BODRF Position
| #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) |
SYS_T::RSTSTS: CPULKRF Mask
| #define SYS_RSTSTS_CPULKRF_Pos (8) |
SYS_T::RSTSTS: CPULKRF Position
| #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
SYS_T::RSTSTS: CPURF Mask
| #define SYS_RSTSTS_CPURF_Pos (7) |
SYS_T::RSTSTS: CPURF Position
| #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
SYS_T::RSTSTS: LVRF Mask
| #define SYS_RSTSTS_LVRF_Pos (3) |
SYS_T::RSTSTS: LVRF Position
| #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
SYS_T::RSTSTS: PINRF Mask
| #define SYS_RSTSTS_PINRF_Pos (1) |
SYS_T::RSTSTS: PINRF Position
| #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
SYS_T::RSTSTS: PORF Mask
| #define SYS_RSTSTS_PORF_Pos (0) |
SYS_T::RSTSTS: PORF Position
| #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
SYS_T::RSTSTS: SYSRF Mask
| #define SYS_RSTSTS_SYSRF_Pos (5) |
SYS_T::RSTSTS: SYSRF Position
| #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
SYS_T::RSTSTS: WDTRF Mask
| #define SYS_RSTSTS_WDTRF_Pos (2) |
SYS_T::RSTSTS: WDTRF Position
| #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) |
SYS_T::SRAM_BISTCTL: CRBIST Mask
| #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) |
SYS_T::SRAM_BISTCTL: CRBIST Position
| #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) |
SYS_T::SRAM_BISTCTL: SRBIST0 Mask
| #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) |
SYS_T::SRAM_BISTCTL: SRBIST0 Position
| #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) |
SYS_T::SRAM_BISTCTL: SRBIST1 Mask
| #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) |
SYS_T::SRAM_BISTCTL: SRBIST1 Position
| #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) |
SYS_T::SRAM_BISTCTL: USBBIST Mask
| #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) |
SYS_T::SRAM_BISTCTL: USBBIST Position
| #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) |
SYS_T::SRAM_BISTSTS: CRBEND Mask
| #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) |
SYS_T::SRAM_BISTSTS: CRBEND Position
| #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) |
SYS_T::SRAM_BISTSTS: CRBISTEF Mask
| #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) |
SYS_T::SRAM_BISTSTS: CRBISTEF Position
| #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) |
SYS_T::SRAM_BISTSTS: SRBEND0 Mask
| #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) |
SYS_T::SRAM_BISTSTS: SRBEND0 Position
| #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) |
SYS_T::SRAM_BISTSTS: SRBEND1 Mask
| #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) |
SYS_T::SRAM_BISTSTS: SRBEND1 Position
| #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) |
SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask
| #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) |
SYS_T::SRAM_BISTSTS: SRBISTEF0 Position
| #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) |
SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask
| #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) |
SYS_T::SRAM_BISTSTS: SRBISTEF1 Position
| #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) |
SYS_T::SRAM_BISTSTS: USBBEF Mask
| #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) |
SYS_T::SRAM_BISTSTS: USBBEF Position
| #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) |
SYS_T::SRAM_BISTSTS: USBBEND Mask
| #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) |
SYS_T::SRAM_BISTSTS: USBBEND Position
| #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) |
SYS_T::USBPHY: LDO33EN Mask
| #define SYS_USBPHY_LDO33EN_Pos (8) |
SYS_T::USBPHY: LDO33EN Position
| #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) |
SYS_T::USBPHY: USBROLE Mask
| #define SYS_USBPHY_USBROLE_Pos (0) |
SYS_T::USBPHY: USBROLE Position
| #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) |
SYS_T::VREFCTL: VREFCTL Mask
| #define SYS_VREFCTL_VREFCTL_Pos (0) |
SYS_T::VREFCTL: VREFCTL Position
| #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
TIMER_T::CAP: CAPDAT Mask
| #define TIMER_CAP_CAPDAT_Pos (0) |
TIMER_T::CAP: CAPDAT Position
| #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) |
TIMER_T::CMP: CMPDAT Mask
| #define TIMER_CMP_CMPDAT_Pos (0) |
TIMER_T::CMP: CMPDAT Position
| #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) |
TIMER_T::CNT: CNT Mask
| #define TIMER_CNT_CNT_Pos (0) |
TIMER_T::CNT: CNT Position
| #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
TIMER_T::CTL: ACTSTS Mask
| #define TIMER_CTL_ACTSTS_Pos (25) |
TIMER_T::CTL: ACTSTS Position
| #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
TIMER_T::CTL: CNTEN Mask
| #define TIMER_CTL_CNTEN_Pos (30) |
TIMER_T::CTL: CNTEN Position
| #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
TIMER_T::CTL: EXTCNTEN Mask
| #define TIMER_CTL_EXTCNTEN_Pos (24) |
TIMER_T::CTL: EXTCNTEN Position
| #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
TIMER_T::CTL: ICEDEBUG Mask
| #define TIMER_CTL_ICEDEBUG_Pos (31) |
TIMER_T::CTL: ICEDEBUG Position
| #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) |
TIMER_T::CTL: INTEN Mask
| #define TIMER_CTL_INTEN_Pos (29) |
TIMER_T::CTL: INTEN Position
| #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
TIMER_T::CTL: OPMODE Mask
| #define TIMER_CTL_OPMODE_Pos (27) |
TIMER_T::CTL: OPMODE Position
| #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) |
TIMER_T::CTL: PSC Mask
| #define TIMER_CTL_PSC_Pos (0) |
@addtogroup TMR_CONST TMR Bit Field Definition Constant Definitions for TMR Controller
TIMER_T::CTL: PSC Position
| #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) |
TIMER_T::CTL: RSTCNT Mask
| #define TIMER_CTL_RSTCNT_Pos (26) |
TIMER_T::CTL: RSTCNT Position
| #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) |
TIMER_T::CTL: TGLPINSEL Mask
| #define TIMER_CTL_TGLPINSEL_Pos (22) |
TIMER_T::CTL: TGLPINSEL Position
| #define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) |
TIMER_T::CTL: TRGEADC Mask
| #define TIMER_CTL_TRGEADC_Pos (21) |
TIMER_T::CTL: TRGEADC Position
| #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) |
TIMER_T::CTL: TRGPWM Mask
| #define TIMER_CTL_TRGPWM_Pos (19) |
TIMER_T::CTL: TRGPWM Position
| #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) |
TIMER_T::CTL: TRGSSEL Mask
| #define TIMER_CTL_TRGSSEL_Pos (18) |
TIMER_T::CTL: TRGSSEL Position
| #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
TIMER_T::CTL: WKEN Mask
| #define TIMER_CTL_WKEN_Pos (23) |
TIMER_T::CTL: WKEN Position
| #define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) |
TIMER_T::CTL: WKTKEN Mask
| #define TIMER_CTL_WKTKEN_Pos (17) |
TIMER_T::CTL: WKTKEN Position
| #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) |
TIMER_T::EINTSTS: CAPIF Mask
| #define TIMER_EINTSTS_CAPIF_Pos (0) |
TIMER_T::EINTSTS: CAPIF Position
| #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) |
TIMER_T::EXTCTL: CAPDBEN Mask
| #define TIMER_EXTCTL_CAPDBEN_Pos (6) |
TIMER_T::EXTCTL: CAPDBEN Position
| #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) |
TIMER_T::EXTCTL: CAPEDGE Mask
| #define TIMER_EXTCTL_CAPEDGE_Pos (1) |
TIMER_T::EXTCTL: CAPEDGE Position
| #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) |
TIMER_T::EXTCTL: CAPEN Mask
| #define TIMER_EXTCTL_CAPEN_Pos (3) |
TIMER_T::EXTCTL: CAPEN Position
| #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) |
TIMER_T::EXTCTL: CAPFUNCS Mask
| #define TIMER_EXTCTL_CAPFUNCS_Pos (4) |
TIMER_T::EXTCTL: CAPFUNCS Position
| #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) |
TIMER_T::EXTCTL: CAPIEN Mask
| #define TIMER_EXTCTL_CAPIEN_Pos (5) |
TIMER_T::EXTCTL: CAPIEN Position
| #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) |
TIMER_T::EXTCTL: CNTDBEN Mask
| #define TIMER_EXTCTL_CNTDBEN_Pos (7) |
TIMER_T::EXTCTL: CNTDBEN Position
| #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) |
TIMER_T::EXTCTL: CNTPHASE Mask
| #define TIMER_EXTCTL_CNTPHASE_Pos (0) |
TIMER_T::EXTCTL: CNTPHASE Position
| #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) |
TIMER_T::INTSTS: TIF Mask
| #define TIMER_INTSTS_TIF_Pos (0) |
TIMER_T::INTSTS: TIF Position
| #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
TIMER_T::INTSTS: TWKF Mask
| #define TIMER_INTSTS_TWKF_Pos (1) |
TIMER_T::INTSTS: TWKF Position
| #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) |
UART_T::ALTCTL: ABRDBITS Mask
| #define UART_ALTCTL_ABRDBITS_Pos (19) |
UART_T::ALTCTL: ABRDBITS Position
| #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) |
UART_T::ALTCTL: ABRDEN Mask
| #define UART_ALTCTL_ABRDEN_Pos (18) |
UART_T::ALTCTL: ABRDEN Position
| #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) |
UART_T::ALTCTL: ABRIF Mask
| #define UART_ALTCTL_ABRIF_Pos (17) |
UART_T::ALTCTL: ABRIF Position
| #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
UART_T::ALTCTL: ADDRDEN Mask
| #define UART_ALTCTL_ADDRDEN_Pos (15) |
UART_T::ALTCTL: ADDRDEN Position
| #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) |
UART_T::ALTCTL: ADDRMV Mask
| #define UART_ALTCTL_ADDRMV_Pos (24) |
UART_T::ALTCTL: ADDRMV Position
| #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) |
UART_T::ALTCTL: BRKFL Mask
| #define UART_ALTCTL_BRKFL_Pos (0) |
UART_T::ALTCTL: BRKFL Position
| #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
UART_T::ALTCTL: LINRXEN Mask
| #define UART_ALTCTL_LINRXEN_Pos (6) |
UART_T::ALTCTL: LINRXEN Position
| #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
UART_T::ALTCTL: LINTXEN Mask
| #define UART_ALTCTL_LINTXEN_Pos (7) |
UART_T::ALTCTL: LINTXEN Position
| #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
UART_T::ALTCTL: RS485AAD Mask
| #define UART_ALTCTL_RS485AAD_Pos (9) |
UART_T::ALTCTL: RS485AAD Position
| #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
UART_T::ALTCTL: RS485AUD Mask
| #define UART_ALTCTL_RS485AUD_Pos (10) |
UART_T::ALTCTL: RS485AUD Position
| #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
UART_T::ALTCTL: RS485NMM Mask
| #define UART_ALTCTL_RS485NMM_Pos (8) |
UART_T::ALTCTL: RS485NMM Position
| #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) |
UART_T::BAUD: BAUDM0 Mask
| #define UART_BAUD_BAUDM0_Pos (28) |
UART_T::BAUD: BAUDM0 Position
| #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) |
UART_T::BAUD: BAUDM1 Mask
| #define UART_BAUD_BAUDM1_Pos (29) |
UART_T::BAUD: BAUDM1 Position
| #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
UART_T::BAUD: BRD Mask
| #define UART_BAUD_BRD_Pos (0) |
UART_T::BAUD: BRD Position
| #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) |
UART_T::BAUD: EDIVM1 Mask
| #define UART_BAUD_EDIVM1_Pos (24) |
UART_T::BAUD: EDIVM1 Position
| #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
UART_T::DAT: DAT Mask
| #define UART_DAT_DAT_Pos (0) |
@addtogroup UART_CONST UART Bit Field Definition Constant Definitions for UART Controller
UART_T::DAT: DAT Position
| #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) |
UART_T::FIFO: RFITL Mask
| #define UART_FIFO_RFITL_Pos (4) |
UART_T::FIFO: RFITL Position
| #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) |
UART_T::FIFO: RTSTRGLV Mask
| #define UART_FIFO_RTSTRGLV_Pos (16) |
UART_T::FIFO: RTSTRGLV Position
| #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) |
UART_T::FIFO: RXOFF Mask
| #define UART_FIFO_RXOFF_Pos (8) |
UART_T::FIFO: RXOFF Position
| #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) |
UART_T::FIFO: RXRST Mask
| #define UART_FIFO_RXRST_Pos (1) |
UART_T::FIFO: RXRST Position
| #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) |
UART_T::FIFO: TXRST Mask
| #define UART_FIFO_TXRST_Pos (2) |
UART_T::FIFO: TXRST Position
| #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) |
UART_T::FIFOSTS: ABRDIF Mask
| #define UART_FIFOSTS_ABRDIF_Pos (1) |
UART_T::FIFOSTS: ABRDIF Position
| #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) |
UART_T::FIFOSTS: ABRDTOIF Mask
| #define UART_FIFOSTS_ABRDTOIF_Pos (2) |
UART_T::FIFOSTS: ABRDTOIF Position
| #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) |
UART_T::FIFOSTS: ADDRDETF Mask
| #define UART_FIFOSTS_ADDRDETF_Pos (3) |
UART_T::FIFOSTS: ADDRDETF Position
| #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
UART_T::FIFOSTS: BIF Mask
| #define UART_FIFOSTS_BIF_Pos (6) |
UART_T::FIFOSTS: BIF Position
| #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
UART_T::FIFOSTS: FEF Mask
| #define UART_FIFOSTS_FEF_Pos (5) |
UART_T::FIFOSTS: FEF Position
| #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
UART_T::FIFOSTS: PEF Mask
| #define UART_FIFOSTS_PEF_Pos (4) |
UART_T::FIFOSTS: PEF Position
| #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
UART_T::FIFOSTS: RXEMPTY Mask
| #define UART_FIFOSTS_RXEMPTY_Pos (14) |
UART_T::FIFOSTS: RXEMPTY Position
| #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
UART_T::FIFOSTS: RXFULL Mask
| #define UART_FIFOSTS_RXFULL_Pos (15) |
UART_T::FIFOSTS: RXFULL Position
| #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
UART_T::FIFOSTS: RXOVIF Mask
| #define UART_FIFOSTS_RXOVIF_Pos (0) |
UART_T::FIFOSTS: RXOVIF Position
| #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) |
UART_T::FIFOSTS: RXPTR Mask
| #define UART_FIFOSTS_RXPTR_Pos (8) |
UART_T::FIFOSTS: RXPTR Position
| #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
UART_T::FIFOSTS: TXEMPTY Mask
| #define UART_FIFOSTS_TXEMPTY_Pos (22) |
UART_T::FIFOSTS: TXEMPTY Position
| #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) |
UART_T::FIFOSTS: TXEMPTYF Mask
| #define UART_FIFOSTS_TXEMPTYF_Pos (28) |
UART_T::FIFOSTS: TXEMPTYF Position
| #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
UART_T::FIFOSTS: TXFULL Mask
| #define UART_FIFOSTS_TXFULL_Pos (23) |
UART_T::FIFOSTS: TXFULL Position
| #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
UART_T::FIFOSTS: TXOVIF Mask
| #define UART_FIFOSTS_TXOVIF_Pos (24) |
UART_T::FIFOSTS: TXOVIF Position
| #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) |
UART_T::FIFOSTS: TXPTR Mask
| #define UART_FIFOSTS_TXPTR_Pos (16) |
UART_T::FIFOSTS: TXPTR Position
| #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) |
UART_T::FUNCSEL: FUNCSEL Mask
| #define UART_FUNCSEL_FUNCSEL_Pos (0) |
UART_T::FUNCSEL: FUNCSEL Position
| #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) |
UART_T::INTEN: ABRIEN Mask
| #define UART_INTEN_ABRIEN_Pos (18) |
UART_T::INTEN: ABRIEN Position
| #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) |
UART_T::INTEN: ATOCTSEN Mask
| #define UART_INTEN_ATOCTSEN_Pos (13) |
UART_T::INTEN: ATOCTSEN Position
| #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) |
UART_T::INTEN: ATORTSEN Mask
| #define UART_INTEN_ATORTSEN_Pos (12) |
UART_T::INTEN: ATORTSEN Position
| #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
UART_T::INTEN: BUFERRIEN Mask
| #define UART_INTEN_BUFERRIEN_Pos (5) |
UART_T::INTEN: BUFERRIEN Position
| #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
UART_T::INTEN: LINIEN Mask
| #define UART_INTEN_LINIEN_Pos (8) |
UART_T::INTEN: LINIEN Position
| #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
UART_T::INTEN: MODEMIEN Mask
| #define UART_INTEN_MODEMIEN_Pos (3) |
UART_T::INTEN: MODEMIEN Position
| #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
UART_T::INTEN: RDAIEN Mask
| #define UART_INTEN_RDAIEN_Pos (0) |
UART_T::INTEN: RDAIEN Position
| #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
UART_T::INTEN: RLSIEN Mask
| #define UART_INTEN_RLSIEN_Pos (2) |
UART_T::INTEN: RLSIEN Position
| #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) |
UART_T::INTEN: RXPDMAEN Mask
| #define UART_INTEN_RXPDMAEN_Pos (15) |
UART_T::INTEN: RXPDMAEN Position
| #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
UART_T::INTEN: RXTOIEN Mask
| #define UART_INTEN_RXTOIEN_Pos (4) |
UART_T::INTEN: RXTOIEN Position
| #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
UART_T::INTEN: THREIEN Mask
| #define UART_INTEN_THREIEN_Pos (1) |
UART_T::INTEN: THREIEN Position
| #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) |
UART_T::INTEN: TOCNTEN Mask
| #define UART_INTEN_TOCNTEN_Pos (11) |
UART_T::INTEN: TOCNTEN Position
| #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) |
UART_T::INTEN: TXPDMAEN Mask
| #define UART_INTEN_TXPDMAEN_Pos (14) |
UART_T::INTEN: TXPDMAEN Position
| #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) |
UART_T::INTEN: WKCTSIEN Mask
| #define UART_INTEN_WKCTSIEN_Pos (9) |
UART_T::INTEN: WKCTSIEN Position
| #define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) |
UART_T::INTEN: WKDATIEN Mask
| #define UART_INTEN_WKDATIEN_Pos (10) |
UART_T::INTEN: WKDATIEN Position
| #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
UART_T::INTSTS: BUFERRIF Mask
| #define UART_INTSTS_BUFERRIF_Pos (5) |
UART_T::INTSTS: BUFERRIF Position
| #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) |
UART_T::INTSTS: BUFERRINT Mask
| #define UART_INTSTS_BUFERRINT_Pos (13) |
UART_T::INTSTS: BUFERRINT Position
| #define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) |
UART_T::INTSTS: CTSWKIF Mask
| #define UART_INTSTS_CTSWKIF_Pos (16) |
UART_T::INTSTS: CTSWKIF Position
| #define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) |
UART_T::INTSTS: DATWKIF Mask
| #define UART_INTSTS_DATWKIF_Pos (17) |
UART_T::INTSTS: DATWKIF Position
| #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) |
UART_T::INTSTS: HWBUFEIF Mask
| #define UART_INTSTS_HWBUFEIF_Pos (21) |
UART_T::INTSTS: HWBUFEIF Position
| #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) |
UART_T::INTSTS: HWBUFEINT Mask
| #define UART_INTSTS_HWBUFEINT_Pos (29) |
UART_T::INTSTS: HWBUFEINT Position
| #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) |
UART_T::INTSTS: HWMODIF Mask
| #define UART_INTSTS_HWMODIF_Pos (19) |
UART_T::INTSTS: HWMODIF Position
| #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) |
UART_T::INTSTS: HWMODINT Mask
| #define UART_INTSTS_HWMODINT_Pos (27) |
UART_T::INTSTS: HWMODINT Position
| #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) |
UART_T::INTSTS: HWRLSIF Mask
| #define UART_INTSTS_HWRLSIF_Pos (18) |
UART_T::INTSTS: HWRLSIF Position
| #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) |
UART_T::INTSTS: HWRLSINT Mask
| #define UART_INTSTS_HWRLSINT_Pos (26) |
UART_T::INTSTS: HWRLSINT Position
| #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) |
UART_T::INTSTS: HWTOIF Mask
| #define UART_INTSTS_HWTOIF_Pos (20) |
UART_T::INTSTS: HWTOIF Position
| #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) |
UART_T::INTSTS: HWTOINT Mask
| #define UART_INTSTS_HWTOINT_Pos (28) |
UART_T::INTSTS: HWTOINT Position
| #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
UART_T::INTSTS: LINIF Mask
| #define UART_INTSTS_LINIF_Pos (7) |
UART_T::INTSTS: LINIF Position
| #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) |
UART_T::INTSTS: LININT Mask
| #define UART_INTSTS_LININT_Pos (15) |
UART_T::INTSTS: LININT Position
| #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
UART_T::INTSTS: MODEMIF Mask
| #define UART_INTSTS_MODEMIF_Pos (3) |
UART_T::INTSTS: MODEMIF Position
| #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) |
UART_T::INTSTS: MODEMINT Mask
| #define UART_INTSTS_MODEMINT_Pos (11) |
UART_T::INTSTS: MODEMINT Position
| #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
UART_T::INTSTS: RDAIF Mask
| #define UART_INTSTS_RDAIF_Pos (0) |
UART_T::INTSTS: RDAIF Position
| #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) |
UART_T::INTSTS: RDAINT Mask
| #define UART_INTSTS_RDAINT_Pos (8) |
UART_T::INTSTS: RDAINT Position
| #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
UART_T::INTSTS: RLSIF Mask
| #define UART_INTSTS_RLSIF_Pos (2) |
UART_T::INTSTS: RLSIF Position
| #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) |
UART_T::INTSTS: RLSINT Mask
| #define UART_INTSTS_RLSINT_Pos (10) |
UART_T::INTSTS: RLSINT Position
| #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
UART_T::INTSTS: RXTOIF Mask
| #define UART_INTSTS_RXTOIF_Pos (4) |
UART_T::INTSTS: RXTOIF Position
| #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) |
UART_T::INTSTS: RXTOINT Mask
| #define UART_INTSTS_RXTOINT_Pos (12) |
UART_T::INTSTS: RXTOINT Position
| #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
UART_T::INTSTS: THREIF Mask
| #define UART_INTSTS_THREIF_Pos (1) |
UART_T::INTSTS: THREIF Position
| #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) |
UART_T::INTSTS: THREINT Mask
| #define UART_INTSTS_THREINT_Pos (9) |
UART_T::INTSTS: THREINT Position
| #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) |
UART_T::INTSTS: WKIF Mask
| #define UART_INTSTS_WKIF_Pos (6) |
UART_T::INTSTS: WKIF Position
| #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
UART_T::IRDA: RXINV Mask
| #define UART_IRDA_RXINV_Pos (6) |
UART_T::IRDA: RXINV Position
| #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
UART_T::IRDA: TXEN Mask
| #define UART_IRDA_TXEN_Pos (1) |
UART_T::IRDA: TXEN Position
| #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
UART_T::IRDA: TXINV Mask
| #define UART_IRDA_TXINV_Pos (5) |
UART_T::IRDA: TXINV Position
| #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
UART_T::LINE: BCB Mask
| #define UART_LINE_BCB_Pos (6) |
UART_T::LINE: BCB Position
| #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
UART_T::LINE: EPE Mask
| #define UART_LINE_EPE_Pos (4) |
UART_T::LINE: EPE Position
| #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
UART_T::LINE: NSB Mask
| #define UART_LINE_NSB_Pos (2) |
UART_T::LINE: NSB Position
| #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
UART_T::LINE: PBE Mask
| #define UART_LINE_PBE_Pos (3) |
UART_T::LINE: PBE Position
| #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
UART_T::LINE: SPE Mask
| #define UART_LINE_SPE_Pos (5) |
UART_T::LINE: SPE Position
| #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
UART_T::LINE: WLS Mask
| #define UART_LINE_WLS_Pos (0) |
UART_T::LINE: WLS Position
| #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) |
UART_T::MODEM: RTS Mask
| #define UART_MODEM_RTS_Pos (1) |
UART_T::MODEM: RTS Position
| #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
UART_T::MODEM: RTSACTLV Mask
| #define UART_MODEM_RTSACTLV_Pos (9) |
UART_T::MODEM: RTSACTLV Position
| #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
UART_T::MODEM: RTSSTS Mask
| #define UART_MODEM_RTSSTS_Pos (13) |
UART_T::MODEM: RTSSTS Position
| #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) |
UART_T::MODEMSTS: CTSACTLV Mask
| #define UART_MODEMSTS_CTSACTLV_Pos (8) |
UART_T::MODEMSTS: CTSACTLV Position
| #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) |
UART_T::MODEMSTS: CTSDETF Mask
| #define UART_MODEMSTS_CTSDETF_Pos (0) |
UART_T::MODEMSTS: CTSDETF Position
| #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) |
UART_T::MODEMSTS: CTSSTS Mask
| #define UART_MODEMSTS_CTSSTS_Pos (4) |
UART_T::MODEMSTS: CTSSTS Position
| #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
UART_T::TOUT: DLY Mask
| #define UART_TOUT_DLY_Pos (8) |
UART_T::TOUT: DLY Position
| #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) |
UART_T::TOUT: TOIC Mask
| #define UART_TOUT_TOIC_Pos (0) |
UART_T::TOUT: TOIC Position
| #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) |
USBD_T::ATTR: BYTEM Mask
| #define USBD_ATTR_BYTEM_Pos (10) |
USBD_T::ATTR: BYTEM Position
| #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) |
USBD_T::ATTR: DPPUEN Mask
| #define USBD_ATTR_DPPUEN_Pos (8) |
USBD_T::ATTR: DPPUEN Position
| #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) |
USBD_T::ATTR: PHYEN Mask
| #define USBD_ATTR_PHYEN_Pos (4) |
USBD_T::ATTR: PHYEN Position
| #define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) |
USBD_T::ATTR: PWRDN Mask
| #define USBD_ATTR_PWRDN_Pos (9) |
USBD_T::ATTR: PWRDN Position
| #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) |
USBD_T::ATTR: RESUME Mask
| #define USBD_ATTR_RESUME_Pos (2) |
USBD_T::ATTR: RESUME Position
| #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) |
USBD_T::ATTR: RWAKEUP Mask
| #define USBD_ATTR_RWAKEUP_Pos (5) |
USBD_T::ATTR: RWAKEUP Position
| #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) |
USBD_T::ATTR: SUSPEND Mask
| #define USBD_ATTR_SUSPEND_Pos (1) |
USBD_T::ATTR: SUSPEND Position
| #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) |
USBD_T::ATTR: TOUT Mask
| #define USBD_ATTR_TOUT_Pos (3) |
USBD_T::ATTR: TOUT Position
| #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) |
USBD_T::ATTR: USBEN Mask
| #define USBD_ATTR_USBEN_Pos (7) |
USBD_T::ATTR: USBEN Position
| #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) |
USBD_T::ATTR: USBRST Mask
| #define USBD_ATTR_USBRST_Pos (0) |
USBD_T::ATTR: USBRST Position
| #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) |
USBD_EP_T::BUFSEG: BUFSEG Mask
| #define USBD_BUFSEG_BUFSEG_Pos (3) |
USBD_EP_T::BUFSEG: BUFSEG Position
| #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) |
USBD_EP_T::CFG: CSTALL Mask
| #define USBD_CFG_CSTALL_Pos (9) |
USBD_EP_T::CFG: CSTALL Position
| #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) |
USBD_EP_T::CFG: DSQSYNC Mask
| #define USBD_CFG_DSQSYNC_Pos (7) |
USBD_EP_T::CFG: DSQSYNC Position
| #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) |
USBD_EP_T::CFG: EPNUM Mask
| #define USBD_CFG_EPNUM_Pos (0) |
USBD_EP_T::CFG: EPNUM Position
| #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) |
USBD_EP_T::CFG: ISOCH Mask
| #define USBD_CFG_ISOCH_Pos (4) |
USBD_EP_T::CFG: ISOCH Position
| #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) |
USBD_EP_T::CFG: STATE Mask
| #define USBD_CFG_STATE_Pos (5) |
USBD_EP_T::CFG: STATE Position
| #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) |
USBD_EP_T::CFGP: CLRRDY Mask
| #define USBD_CFGP_CLRRDY_Pos (0) |
USBD_EP_T::CFGP: CLRRDY Position
| #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) |
USBD_EP_T::CFGP: SSTALL Mask
| #define USBD_CFGP_SSTALL_Pos (1) |
USBD_EP_T::CFGP: SSTALL Position
| #define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) |
USBD_T::EPSTS: EPSTS0 Mask
| #define USBD_EPSTS_EPSTS0_Pos (8) |
USBD_T::EPSTS: EPSTS0 Position
| #define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) |
USBD_T::EPSTS: EPSTS1 Mask
| #define USBD_EPSTS_EPSTS1_Pos (11) |
USBD_T::EPSTS: EPSTS1 Position
| #define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) |
USBD_T::EPSTS: EPSTS2 Mask
| #define USBD_EPSTS_EPSTS2_Pos (14) |
USBD_T::EPSTS: EPSTS2 Position
| #define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) |
USBD_T::EPSTS: EPSTS3 Mask
| #define USBD_EPSTS_EPSTS3_Pos (17) |
USBD_T::EPSTS: EPSTS3 Position
| #define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) |
USBD_T::EPSTS: EPSTS4 Mask
| #define USBD_EPSTS_EPSTS4_Pos (20) |
USBD_T::EPSTS: EPSTS4 Position
| #define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) |
USBD_T::EPSTS: EPSTS5 Mask
| #define USBD_EPSTS_EPSTS5_Pos (23) |
USBD_T::EPSTS: EPSTS5 Position
| #define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) |
USBD_T::EPSTS: EPSTS6 Mask
| #define USBD_EPSTS_EPSTS6_Pos (26) |
USBD_T::EPSTS: EPSTS6 Position
| #define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) |
USBD_T::EPSTS: EPSTS7 Mask
| #define USBD_EPSTS_EPSTS7_Pos (29) |
USBD_T::EPSTS: EPSTS7 Position
| #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) |
USBD_T::EPSTS: OV Mask
| #define USBD_EPSTS_OV_Pos (7) |
USBD_T::EPSTS: OV Position
| #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
USBD_T::FADDR: FADDR Mask
| #define USBD_FADDR_FADDR_Pos (0) |
USBD_T::FADDR: FADDR Position
| #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) |
USBD_T::INTEN: BUSIEN Mask
| #define USBD_INTEN_BUSIEN_Pos (0) |
@addtogroup USB_CONST USB Bit Field Definition Constant Definitions for USB Controller
USBD_T::INTEN: BUSIEN Position
| #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) |
USBD_T::INTEN: INNAKEN Mask
| #define USBD_INTEN_INNAKEN_Pos (15) |
USBD_T::INTEN: INNAKEN Position
| #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) |
USBD_T::INTEN: NEVWKIEN Mask
| #define USBD_INTEN_NEVWKIEN_Pos (3) |
USBD_T::INTEN: NEVWKIEN Position
| #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) |
USBD_T::INTEN: USBIEN Mask
| #define USBD_INTEN_USBIEN_Pos (1) |
USBD_T::INTEN: USBIEN Position
| #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) |
USBD_T::INTEN: VBDETIEN Mask
| #define USBD_INTEN_VBDETIEN_Pos (2) |
USBD_T::INTEN: VBDETIEN Position
| #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) |
USBD_T::INTEN: WKEN Mask
| #define USBD_INTEN_WKEN_Pos (8) |
USBD_T::INTEN: WKEN Position
| #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) |
USBD_T::INTSTS: BUSIF Mask
| #define USBD_INTSTS_BUSIF_Pos (0) |
USBD_T::INTSTS: BUSIF Position
| #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) |
USBD_T::INTSTS: EPEVT0 Mask
| #define USBD_INTSTS_EPEVT0_Pos (16) |
USBD_T::INTSTS: EPEVT0 Position
| #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) |
USBD_T::INTSTS: EPEVT1 Mask
| #define USBD_INTSTS_EPEVT1_Pos (17) |
USBD_T::INTSTS: EPEVT1 Position
| #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) |
USBD_T::INTSTS: EPEVT2 Mask
| #define USBD_INTSTS_EPEVT2_Pos (18) |
USBD_T::INTSTS: EPEVT2 Position
| #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) |
USBD_T::INTSTS: EPEVT3 Mask
| #define USBD_INTSTS_EPEVT3_Pos (19) |
USBD_T::INTSTS: EPEVT3 Position
| #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) |
USBD_T::INTSTS: EPEVT4 Mask
| #define USBD_INTSTS_EPEVT4_Pos (20) |
USBD_T::INTSTS: EPEVT4 Position
| #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) |
USBD_T::INTSTS: EPEVT5 Mask
| #define USBD_INTSTS_EPEVT5_Pos (21) |
USBD_T::INTSTS: EPEVT5 Position
| #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) |
USBD_T::INTSTS: EPEVT6 Mask
| #define USBD_INTSTS_EPEVT6_Pos (22) |
USBD_T::INTSTS: EPEVT6 Position
| #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) |
USBD_T::INTSTS: EPEVT7 Mask
| #define USBD_INTSTS_EPEVT7_Pos (23) |
USBD_T::INTSTS: EPEVT7 Position
| #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) |
USBD_T::INTSTS: NEVWKIF Mask
| #define USBD_INTSTS_NEVWKIF_Pos (3) |
USBD_T::INTSTS: NEVWKIF Position
| #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) |
USBD_T::INTSTS: SETUP Mask
| #define USBD_INTSTS_SETUP_Pos (31) |
USBD_T::INTSTS: SETUP Position
| #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) |
USBD_T::INTSTS: SOFIF Mask
| #define USBD_INTSTS_SOFIF_Pos (4) |
USBD_T::INTSTS: SOFIF Position
| #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) |
USBD_T::INTSTS: USBIF Mask
| #define USBD_INTSTS_USBIF_Pos (1) |
USBD_T::INTSTS: USBIF Position
| #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) |
USBD_T::INTSTS: VBDETIF Mask
| #define USBD_INTSTS_VBDETIF_Pos (2) |
USBD_T::INTSTS: VBDETIF Position
| #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) |
USBD_EP_T::MXPLD: MXPLD Mask
| #define USBD_MXPLD_MXPLD_Pos (0) |
USBD_EP_T::MXPLD: MXPLD Position
| #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) |
USBD_T::SE0: SE0 Mask
| #define USBD_SE0_SE0_Pos (0) |
USBD_T::SE0: SE0 Position
| #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) |
USBD_T::STBUFSEG: STBUFSEG Mask
| #define USBD_STBUFSEG_STBUFSEG_Pos (3) |
USBD_T::STBUFSEG: STBUFSEG Position
| #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) |
USBD_T::VBUSDET: VBUSDET Mask
| #define USBD_VBUSDET_VBUSDET_Pos (0) |
USBD_T::VBUSDET: VBUSDET Position
| #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) |
USBH_T::HcBulkCurrentED: BCED Mask
| #define USBH_HcBulkCurrentED_BCED_Pos (4) |
USBH_T::HcBulkCurrentED: BCED Position
| #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) |
USBH_T::HcBulkHeadED: BHED Mask
| #define USBH_HcBulkHeadED_BHED_Pos (4) |
USBH_T::HcBulkHeadED: BHED Position
| #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) |
USBH_T::HcCommandStatus: BLF Mask
| #define USBH_HcCommandStatus_BLF_Pos (2) |
USBH_T::HcCommandStatus: BLF Position
| #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) |
USBH_T::HcCommandStatus: CLF Mask
| #define USBH_HcCommandStatus_CLF_Pos (1) |
USBH_T::HcCommandStatus: CLF Position
| #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) |
USBH_T::HcCommandStatus: HCR Mask
| #define USBH_HcCommandStatus_HCR_Pos (0) |
USBH_T::HcCommandStatus: HCR Position
| #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) |
USBH_T::HcCommandStatus: SOC Mask
| #define USBH_HcCommandStatus_SOC_Pos (16) |
USBH_T::HcCommandStatus: SOC Position
| #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) |
USBH_T::HcControl: BLE Mask
| #define USBH_HcControl_BLE_Pos (5) |
USBH_T::HcControl: BLE Position
| #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) |
USBH_T::HcControl: CBSR Mask
| #define USBH_HcControl_CBSR_Pos (0) |
USBH_T::HcControl: CBSR Position
| #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) |
USBH_T::HcControl: CLE Mask
| #define USBH_HcControl_CLE_Pos (4) |
USBH_T::HcControl: CLE Position
| #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) |
USBH_T::HcControl: HCFS Mask
| #define USBH_HcControl_HCFS_Pos (6) |
USBH_T::HcControl: HCFS Position
| #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) |
USBH_T::HcControl: IE Mask
| #define USBH_HcControl_IE_Pos (3) |
USBH_T::HcControl: IE Position
| #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) |
USBH_T::HcControl: CBSR Mask
| #define USBH_HcControl_PLE_Pos (2) |
USBH_T::HcControl: CBSR Position
| #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) |
USBH_T::HcControlCurrentED: CCED Mask
| #define USBH_HcControlCurrentED_CCED_Pos (4) |
USBH_T::HcControlCurrentED: CCED Position
| #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) |
USBH_T::HcControlHeadED: CHED Mask
| #define USBH_HcControlHeadED_CHED_Pos (4) |
USBH_T::HcControlHeadED: CHED Position
| #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) |
USBH_T::HcDoneHead: DH Mask
| #define USBH_HcDoneHead_DH_Pos (4) |
USBH_T::HcDoneHead: DH Position
| #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) |
USBH_T::HcFmInterval: FI Mask
| #define USBH_HcFmInterval_FI_Pos (0) |
USBH_T::HcFmInterval: FI Position
| #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) |
USBH_T::HcFmInterval: FIT Mask
| #define USBH_HcFmInterval_FIT_Pos (31) |
USBH_T::HcFmInterval: FIT Position
| #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) |
USBH_T::HcFmInterval: FSMPS Mask
| #define USBH_HcFmInterval_FSMPS_Pos (16) |
USBH_T::HcFmInterval: FSMPS Position
| #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) |
USBH_T::HcFmNumber: FN Mask
| #define USBH_HcFmNumber_FN_Pos (0) |
USBH_T::HcFmNumber: FN Position
| #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) |
USBH_T::HcFmRemaining: FR Mask
| #define USBH_HcFmRemaining_FR_Pos (0) |
USBH_T::HcFmRemaining: FR Position
| #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) |
USBH_T::HcFmRemaining: FRT Mask
| #define USBH_HcFmRemaining_FRT_Pos (31) |
USBH_T::HcFmRemaining: FRT Position
| #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) |
USBH_T::HcHCCA: HCCA Mask
| #define USBH_HcHCCA_HCCA_Pos (8) |
USBH_T::HcHCCA: HCCA Position
| #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) |
USBH_T::HcInterruptDisable: FNO Mask
| #define USBH_HcInterruptDisable_FNO_Pos (5) |
USBH_T::HcInterruptDisable: FNO Position
| #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) |
USBH_T::HcInterruptDisable: MIE Mask
| #define USBH_HcInterruptDisable_MIE_Pos (31) |
USBH_T::HcInterruptDisable: MIE Position
| #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) |
USBH_T::HcInterruptDisable: RD Mask
| #define USBH_HcInterruptDisable_RD_Pos (3) |
USBH_T::HcInterruptDisable: RD Position
| #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) |
USBH_T::HcInterruptDisable: RHSC Mask
| #define USBH_HcInterruptDisable_RHSC_Pos (6) |
USBH_T::HcInterruptDisable: RHSC Position
| #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) |
USBH_T::HcInterruptDisable: SF Mask
| #define USBH_HcInterruptDisable_SF_Pos (2) |
USBH_T::HcInterruptDisable: SF Position
| #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) |
USBH_T::HcInterruptDisable: SO Mask
| #define USBH_HcInterruptDisable_SO_Pos (0) |
USBH_T::HcInterruptDisable: SO Position
| #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) |
USBH_T::HcInterruptDisable: WDH Mask
| #define USBH_HcInterruptDisable_WDH_Pos (1) |
USBH_T::HcInterruptDisable: WDH Position
| #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) |
USBH_T::HcInterruptEnable: FNO Mask
| #define USBH_HcInterruptEnable_FNO_Pos (5) |
USBH_T::HcInterruptEnable: FNO Position
| #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) |
USBH_T::HcInterruptEnable: MIE Mask
| #define USBH_HcInterruptEnable_MIE_Pos (31) |
USBH_T::HcInterruptEnable: MIE Position
| #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) |
USBH_T::HcInterruptEnable: RD Mask
| #define USBH_HcInterruptEnable_RD_Pos (3) |
USBH_T::HcInterruptEnable: RD Position
| #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) |
USBH_T::HcInterruptEnable: RHSC Mask
| #define USBH_HcInterruptEnable_RHSC_Pos (6) |
USBH_T::HcInterruptEnable: RHSC Position
| #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) |
USBH_T::HcInterruptEnable: SF Mask
| #define USBH_HcInterruptEnable_SF_Pos (2) |
USBH_T::HcInterruptEnable: SF Position
| #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) |
USBH_T::HcInterruptEnable: SO Mask
| #define USBH_HcInterruptEnable_SO_Pos (0) |
USBH_T::HcInterruptEnable: SO Position
| #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) |
USBH_T::HcInterruptEnable: WDH Mask
| #define USBH_HcInterruptEnable_WDH_Pos (1) |
USBH_T::HcInterruptEnable: WDH Position
| #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) |
USBH_T::HcInterruptStatus: FNO Mask
| #define USBH_HcInterruptStatus_FNO_Pos (5) |
USBH_T::HcInterruptStatus: FNO Position
| #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) |
USBH_T::HcInterruptStatus: RD Mask
| #define USBH_HcInterruptStatus_RD_Pos (3) |
USBH_T::HcInterruptStatus: RD Position
| #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) |
USBH_T::HcInterruptStatus: RHSC Mask
| #define USBH_HcInterruptStatus_RHSC_Pos (6) |
USBH_T::HcInterruptStatus: RHSC Position
| #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) |
USBH_T::HcInterruptStatus: SF Mask
| #define USBH_HcInterruptStatus_SF_Pos (2) |
USBH_T::HcInterruptStatus: SF Position
| #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) |
USBH_T::HcInterruptStatus: SO Mask
| #define USBH_HcInterruptStatus_SO_Pos (0) |
USBH_T::HcInterruptStatus: SO Position
| #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) |
USBH_T::HcInterruptStatus: WDH Mask
| #define USBH_HcInterruptStatus_WDH_Pos (1) |
USBH_T::HcInterruptStatus: WDH Position
| #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) |
USBH_T::HcLSThreshold: LST Mask
| #define USBH_HcLSThreshold_LST_Pos (0) |
USBH_T::HcLSThreshold: LST Position
| #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) |
USBH_T::HcMiscControl: ABORT Mask
| #define USBH_HcMiscControl_ABORT_Pos (1) |
USBH_T::HcMiscControl: ABORT Position
| #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) |
USBH_T::HcMiscControl: DPRT1 Mask
| #define USBH_HcMiscControl_DPRT1_Pos (16) |
USBH_T::HcMiscControl: DPRT1 Position
| #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) |
USBH_T::HcMiscControl: OCAL Mask
| #define USBH_HcMiscControl_OCAL_Pos (3) |
USBH_T::HcMiscControl: OCAL Position
| #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) |
USBH_T::HcPeriodCurrentED: PCED Mask
| #define USBH_HcPeriodCurrentED_PCED_Pos (4) |
USBH_T::HcPeriodCurrentED: PCED Position
| #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) |
USBH_T::HcPeriodicStart: PS Mask
| #define USBH_HcPeriodicStart_PS_Pos (0) |
USBH_T::HcPeriodicStart: PS Position
| #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) |
USBH_T::HcPhyControl: STBYEN Mask
| #define USBH_HcPhyControl_STBYEN_Pos (27) |
USBH_T::HcPhyControl: STBYEN Position
| #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) |
USBH_T::HcRevision: REV Mask
| #define USBH_HcRevision_REV_Pos (0) |
@addtogroup USBH_CONST USBH Bit Field Definition Constant Definitions for USBH Controller
USBH_T::HcRevision: REV Position
| #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) |
USBH_T::HcRhDescriptorA: NDP Mask
| #define USBH_HcRhDescriptorA_NDP_Pos (0) |
USBH_T::HcRhDescriptorA: NDP Position
| #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) |
USBH_T::HcRhDescriptorA: NOCP Mask
| #define USBH_HcRhDescriptorA_NOCP_Pos (12) |
USBH_T::HcRhDescriptorA: NOCP Position
| #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) |
USBH_T::HcRhDescriptorA: OCPM Mask
| #define USBH_HcRhDescriptorA_OCPM_Pos (11) |
USBH_T::HcRhDescriptorA: OCPM Position
| #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) |
USBH_T::HcRhDescriptorA: PSM Mask
| #define USBH_HcRhDescriptorA_PSM_Pos (8) |
USBH_T::HcRhDescriptorA: PSM Position
| #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) |
USBH_T::HcRhDescriptorB: PPCM Mask
| #define USBH_HcRhDescriptorB_PPCM_Pos (16) |
USBH_T::HcRhDescriptorB: PPCM Position
| #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) |
USBH_T::HcRhPortStatus: CCS Mask
| #define USBH_HcRhPortStatus_CCS_Pos (0) |
USBH_T::HcRhPortStatus: CCS Position
| #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) |
USBH_T::HcRhPortStatus: CSC Mask
| #define USBH_HcRhPortStatus_CSC_Pos (16) |
USBH_T::HcRhPortStatus: CSC Position
| #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) |
USBH_T::HcRhPortStatus: LSDA Mask
| #define USBH_HcRhPortStatus_LSDA_Pos (9) |
USBH_T::HcRhPortStatus: LSDA Position
| #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) |
USBH_T::HcRhPortStatus: OCIC Mask
| #define USBH_HcRhPortStatus_OCIC_Pos (19) |
USBH_T::HcRhPortStatus: OCIC Position
| #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) |
USBH_T::HcRhPortStatus: PES Mask
| #define USBH_HcRhPortStatus_PES_Pos (1) |
USBH_T::HcRhPortStatus: PES Position
| #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) |
USBH_T::HcRhPortStatus: PESC Mask
| #define USBH_HcRhPortStatus_PESC_Pos (17) |
USBH_T::HcRhPortStatus: PESC Position
| #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) |
USBH_T::HcRhPortStatus: POCI Mask
| #define USBH_HcRhPortStatus_POCI_Pos (3) |
USBH_T::HcRhPortStatus: POCI Position
| #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) |
USBH_T::HcRhPortStatus: PPS Mask
| #define USBH_HcRhPortStatus_PPS_Pos (8) |
USBH_T::HcRhPortStatus: PPS Position
| #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) |
USBH_T::HcRhPortStatus: PRS Mask
| #define USBH_HcRhPortStatus_PRS_Pos (4) |
USBH_T::HcRhPortStatus: PRS Position
| #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) |
USBH_T::HcRhPortStatus: PRSC Mask
| #define USBH_HcRhPortStatus_PRSC_Pos (20) |
USBH_T::HcRhPortStatus: PRSC Position
| #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) |
USBH_T::HcRhPortStatus: PSS Mask
| #define USBH_HcRhPortStatus_PSS_Pos (2) |
USBH_T::HcRhPortStatus: PSS Position
| #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) |
USBH_T::HcRhPortStatus: PSSC Mask
| #define USBH_HcRhPortStatus_PSSC_Pos (18) |
USBH_T::HcRhPortStatus: PSSC Position
| #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) |
USBH_T::HcRhStatus: CRWE Mask
| #define USBH_HcRhStatus_CRWE_Pos (31) |
USBH_T::HcRhStatus: CRWE Position
| #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) |
USBH_T::HcRhStatus: DRWE Mask
| #define USBH_HcRhStatus_DRWE_Pos (15) |
USBH_T::HcRhStatus: DRWE Position
| #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) |
USBH_T::HcRhStatus: LPS Mask
| #define USBH_HcRhStatus_LPS_Pos (0) |
USBH_T::HcRhStatus: LPS Position
| #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) |
USBH_T::HcRhStatus: LPSC Mask
| #define USBH_HcRhStatus_LPSC_Pos (16) |
USBH_T::HcRhStatus: LPSC Position
| #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) |
USBH_T::HcRhStatus: OCI Mask
| #define USBH_HcRhStatus_OCI_Pos (1) |
USBH_T::HcRhStatus: OCI Position
| #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) |
USBH_T::HcRhStatus: OCIC Mask
| #define USBH_HcRhStatus_OCIC_Pos (17) |
USBH_T::HcRhStatus: OCIC Position
| #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) |
WDT_T::ALTCTL: RSTDSEL Mask
| #define WDT_ALTCTL_RSTDSEL_Pos (0) |
WDT_T::ALTCTL: RSTDSEL Position
| #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) |
WDT_T::CTL: ICEDEBUG Mask
| #define WDT_CTL_ICEDEBUG_Pos (31) |
WDT_T::CTL: ICEDEBUG Position
| #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) |
WDT_T::CTL: IF Mask
| #define WDT_CTL_IF_Pos (3) |
WDT_T::CTL: IF Position
| #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) |
WDT_T::CTL: INTEN Mask
| #define WDT_CTL_INTEN_Pos (6) |
WDT_T::CTL: INTEN Position
| #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
WDT_T::CTL: RSTCNT Mask
| #define WDT_CTL_RSTCNT_Pos (0) |
@addtogroup WDT_CONST WDT Bit Field Definition Constant Definitions for WDT Controller
WDT_T::CTL: RSTCNT Position
| #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
WDT_T::CTL: RSTEN Mask
| #define WDT_CTL_RSTEN_Pos (1) |
WDT_T::CTL: RSTEN Position
| #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) |
WDT_T::CTL: RSTF Mask
| #define WDT_CTL_RSTF_Pos (2) |
WDT_T::CTL: RSTF Position
| #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) |
WDT_T::CTL: TOUTSEL Mask
| #define WDT_CTL_TOUTSEL_Pos (8) |
WDT_T::CTL: TOUTSEL Position
| #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
WDT_T::CTL: WDTEN Mask
| #define WDT_CTL_WDTEN_Pos (7) |
WDT_T::CTL: WDTEN Position
| #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
WDT_T::CTL: WKEN Mask
| #define WDT_CTL_WKEN_Pos (4) |
WDT_T::CTL: WKEN Position
| #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) |
WDT_T::CTL: WKF Mask
| #define WDT_CTL_WKF_Pos (5) |
WDT_T::CTL: WKF Position
| #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) |
WWDT_T::CNT: CNTDAT Mask
| #define WWDT_CNT_CNTDAT_Pos (0) |
WWDT_T::CNT: CNTDAT Position
| #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) |
WWDT_T::CTL: CMPDAT Mask
| #define WWDT_CTL_CMPDAT_Pos (16) |
WWDT_T::CTL: CMPDAT Position
| #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) |
WWDT_T::CTL: ICEDEBUG Mask
| #define WWDT_CTL_ICEDEBUG_Pos (31) |
WWDT_T::CTL: ICEDEBUG Position
| #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) |
WWDT_T::CTL: INTEN Mask
| #define WWDT_CTL_INTEN_Pos (1) |
WWDT_T::CTL: INTEN Position
| #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) |
WWDT_T::CTL: PSCSEL Mask
| #define WWDT_CTL_PSCSEL_Pos (8) |
WWDT_T::CTL: PSCSEL Position
| #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
WWDT_T::CTL: WWDTEN Mask
| #define WWDT_CTL_WWDTEN_Pos (0) |
WWDT_T::CTL: WWDTEN Position
| #define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) |
WWDT_T::RLDCNT: WWDT_RLDCNT Mask
| #define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) |
@addtogroup WWDT_CONST WWDT Bit Field Definition Constant Definitions for WWDT Controller
WWDT_T::RLDCNT: WWDT_RLDCNT Position
| #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
WWDT_T::STATUS: WWDTIF Mask
| #define WWDT_STATUS_WWDTIF_Pos (0) |
WWDT_T::STATUS: WWDTIF Position
| #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
WWDT_T::STATUS: WWDTRF Mask
| #define WWDT_STATUS_WWDTRF_Pos (1) |
WWDT_T::STATUS: WWDTRF Position